NXP Semiconductors MPC5644A, Reference Manual, Page: 1413 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1413
• Address Offset: 0x18
• Reset Value: 0xFFFF_FFFF
32.4.5.7 Error Counter Register (ECR)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error
Counter (TXECNT) and Receive Error Counter (RXECNT)
. The rules for increasing and decreasing these
counters are described in the CAN protocol and are completely implemented in the FlexCAN module.
Both counters are read only except in Freeze Mode, where they can be written by the CPU.
Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock domains
is executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error
Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when
in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of TXECNT or RXECNT increases to be greater than or equal to 128, ESR[FLTCONF]
is updated to reflect ‘Error Passive’ state.
• If the FlexCAN state is ‘Error Passive’, and either TXECNT or RXECNT decrements to a value
less than or equal to 127 while the other already satisfies this condition, ESR[FLTCONF] is
updated to reflect ‘Error Active’ state.
• If the value of TXECNT increases to be greater than 255, ESR[FLTCONF] is updated to reflect
‘Bus Off’ state, and an interrupt may be issued. The value of TXECNT is then reset to zero.
• If FlexCAN is in ‘Bus Off’ state, then TXECNT is cascaded together with another internal counter
to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECNT is
reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps
around while incrementing the TXECNT. When TXECNT reaches the value of 128,
ESR[FLTCONF] is updated to be ‘Error Active’ and both error counters are reset to zero. At any
instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal
counter resets itself to zero without affecting the TXECNT value.
• If during system start-up, only one node is operating, then its TXECNT increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by ESR[ACKERR]). After the
transition to ‘Error Passive’ state, the TXECNT does not increment anymore by acknowledge
errors. Therefore the device never goes to the ‘Bus Off’ state.
• If the RXECNT increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to ‘Error Active’ state.