NXP Semiconductors MPC5644A, Reference Manual, Page: 107 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 107
5.3.2 Block diagram
Figure 5-1. System clock diagram
Figure 5-2. FMPLL
5.3.3 System clock sources
The on-chip MHz oscillator, PLL and the top level pin are the possible sources of system clock. The system
clock can be generated using any of the following options:
• PLL disabled
— MHz crystal oscillator with crystal as the reference
— MHz crystal oscillator bypassed
• PLL enabled
— MHz crystal oscillator (with crystal as the reference) output used as PLL reference frequency
— MHz crystal oscillator (bypassed) output used as PLL reference frequency
0
1
1
0
XTAL OSC
FMPLL
XTAL
EXTAL
PLLREF
clkcfg[0]
SYSDIV
/2, /4, /8, /16
bypass_sysdiv
siu_system_div[1:0]
IDF
PD
ODF NDIV Lock
Control & Status Registers
PHI
CLKIN
Clock Quality Monitor
(CQM)
loss of
VCO loss of
Reference
system
clock
RCOSC
PFD
Charge pump
Low Pass Filter
VCO
/NDIV
/IDF
CLKIN
/ODF
FMPLL
PHI
FM
Controller
/6
PHI1