NXP Semiconductors MPC5644A, Reference Manual, Page: 390 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
390 Freescale Semiconductor
16.6.4 Reset Status Register (SIU_RSR)
The Reset Status Register (SIU_RSR) reflects the most recent source, or sources, of reset. This register
contains one bit for each reset source, except JTAG reset. A bit set to logic one indicates the type of reset
that occurred. Simultaneous reset requests cause more than one bit to set at the same time. Once set, the
reset source bits in the SIU_RSR remain set until another reset occurs. A Software External Reset causes
the SERF bit to be set, but no previously set bits in the SIU_RSR will be cleared.
The unidirectional mode of reset operation is implemented, all registers named Mode 1 are implemented.
Figure 16-4. Reset Status Register (SIU_RSR)
3h 320 KB/384 KB 1024 KB
4h 512 KB 1.5 MB
5h 768 KB 2 MB
6h 1024 KB 3 MB
7h 1.5 MB 4 MB
8h 2 MB 6 MB
9h 3 MB 8 MB
SI 0xC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PORS ERS LLRS LCRS WDRS 0 SWTRS 0 0 0 0 0 0 0 SSRS SERF
W
Reset
1
1
The reset values for this register are defined for power-on reset only.
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
WKPC
FG
0 0 0 0 0 0 0 0 0 0 0 ABR BOOTCFG
[0–1]
RGF
W
Reset
1
U
2
2
The reset value of this bit is determined by the value latched on the associated pin at the negation of the last reset.
0 0 0 0 0 0 0 0 0 0 0 U
3
3
The reset value of this bit is determined by the inverse of the value latched on the associated EVTO pin.
0 0 0
= Unimplemented or Reserved
Table 16-7. Memory size core dependency (continued)
PARTNUM field z0, z1 z3, z4, z5