NXP Semiconductors MPC5644A, Reference Manual, Page: 1265 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1265
only valid in conjunction with master mode. See Section 1.5.4, “Combined Serial Interface (CSI)
Configuration,” for more details..
TSB mode sets some limitations on transfer attributes:
• Clock phase is forced to be CPHA = 1 and the CPHA bit setting has no effect.
• PCS lines are driven at the driving edge of the SCK clock together with SOUT, so PCS assertion
and negation delays control is unavailable and PCSSCK, PASC, CSSCK and ASC fields have no
effect.
• Delay after transfer can be set from 1 to 64 serial clocks with help of PDT and DT fields.
Address: DSP 0xC–DSP 0x28
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
DBR FMSZ CPOL CPHA LSBFE PCSSCK PASC PDT PBR
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CSSCK ASC DT BR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-8. DSPI Clock and Transfer Attributes Register 0–7 (DSPI_CTAR0–DSPI_CTAR7) in the master
mode
Address: DSP 0xC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FMSZ CPOL CPHA PE PP Not used
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Not used
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-9. DSPI Clock and Transfer Attributes Register 0 (DSPI_CTAR0) in the slave mode