NXP Semiconductors MPC5644A, Reference Manual, Page: 1305 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1305
clock polarity, clock phase and number of bits to transfer must be identical for the master and the slave
devices to ensure proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified Transfer format with CPHA = 0
• Modified Transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPI_MCR selects between Classic SPI
Format and Modified Transfer Format.
In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. See
Section 30.9.6.5, Continuous selection format , for details.
30.9.6.1 Classic SPI transfer format (CPHA = 0)
The transfer format shown in Figure 30-38 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered
SCK edges.