NXP Semiconductors MPC5644A, Reference Manual, Page: 1083 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1083
• A time stamp. In this case, the stored 16-bit data is the value of the time base counter latched when
the EQADC detects the end of the analog input voltage sampling. For details see
Section 25.6.6.4,
Time Stamp Feature .
• A conversion result, coming directly from the ADCs. In this case, the stored 16-bit data contains a
right justified 14-bit result data. The conversion result can be calibrated or not depending on the
status of CAL bit in the command that requested the conversion
1
. When the CAL bit is negated,
this 14-bit data is obtained by executing a 2-bit left-shift on the 12-bit data resultant from the
resolution adjustment on the 8 or 10 or 12-bit data received from the ADC. The resolution
adjustment consists of changing the conversion result input from 8, 10 or 12 bits right aligned to a
12-bit word left aligned - refer to
Section 25.6.6.6, ADC resolution selection feature , for details.
When the CAL bit is asserted, this 14-bit data is the result of the calculations performed in the
EQADC MAC unit using the 12-bit data result of the resolution adjustment and the calibration
constants GCC and OCC, or ALTGCC and ALTOCC - refer to
Section 25.6.6.7, ADC Calibration
Feature , for details. Then, this 14-bit data is further formatted into a 16-bit format according to the
status of the FMT bit in conversion command of the standard configuration or FFMT bit in the
conversion command of the alternate configurations
2
. When FMT/FFMT is asserted, the 14-bit
result data is reformatted to look as if it was measured against an imaginary ground at VREF/2 (the
MSB bit of the 14-bit result is inverted), and is sign-extended to a 16-bit format as in
Figure 25-54 .
When FMT/FFMT is negated, the EQADC zero-extends the 14-bit result data to a 16-bit format as
in
Figure 25-55 . Correspondence between the analog voltage in a channel and the calculated digital
values is shown in Table 25-58 .
1. In case the conversion result is routed through an on-chip DSP via side interface, the calibration is applied before the data
is sent to the DSP.
2. For simplicity, the following text will refer to FMT only, but when using alternate configurations, refer to Section , Conversion
Command Format for Alternate Configurations .
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIGN_EXT RESOLUTION ADJUSTED CONVERSION_RESULT (With inverted MSB bit)
ADC Result
Figure 25-54. ADC Result Format when FMT=1 (Right Justified Signed)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 RESOLUTION ADJUSTED CONVERSION_RESULT
ADC Result
Figure 25-55. ADC Result Format when FMT=0 (Right Justified Unsigned)