NXP Semiconductors MPC5644A, Reference Manual, Page: 161 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 161
8.3.2.14 eDMA Error Registers (EDMA_ERH, EDMA_ERL)
Register EDMA_ERH and EDMA_ERL provide a bitmap for the 32 channels signaling the presence of
an error for each channel. EDMA_ERH supports channels 63–32 (for eDMA) and EDMA_ERL maps to
channels 31-0.
The DMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across
32 (64 for eDMA) channels to form an error interrupt request, which is then routed to the interrupt
controller. During the execution of the interrupt service routine associated with any eDMA errors, it is
software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a write
to the EDMA_CER in the interrupt service routine is used for this purpose. The normal eDMA channel
completion indicators, setting the transfer control descriptor DONE flag and the possible assertion of an
interrupt request, are not affected when an error is detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the EDMA_EEIR. Bit EDMA_ESR[VLD] is a logical OR of all bits in this
register and it provides a single bit indication of any errors. The state of any given channel’s error
indicators is affected by writes to this register; it is also affected by writes to the EDMA_CER. On writes
to EDMA_ERH or EDMA_ERL, a ‘1’ in any bit position clears the corresponding channel’s error status.
A ‘0’ in any bit position has no effect on the corresponding channel’s current error status. The
EDMA_CER is provided so the error indicator for a single channel can be cleared.
Address: EDM 0x0024 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
3
1
INT
3
0
INT
2
9
INT
2
8
INT
2
7
INT
2
6
INT
2
5
INT
2
4
INT
2
3
INT
2
2
INT
2
1
INT
2
0
INT
1
9
INT
1
8
INT
1
7
INT
1
6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IN
T15
IN
T14
IN
T13
IN
T12
INT1
1
IN
T10
IN
T09
IN
T08
IN
T07
IN
T06
IN
T05
IN
T04
IN
T03
IN
T02
IN
T01
IN
T00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-17. eDMA Interrupt Request Register (EDMA_IRQRL)
Table 8-15. EDMA_IRQRL field descriptions
Field Description
0–31
INT
n
eDMA Interrupt Request n
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.