NXP Semiconductors MPC5644A, Reference Manual, Page: 1238 / 1735

Cyclic Redundancy Checker (CRC) Unit
MPC5644A Microcontroller Reference Manual, Rev. 6
1238 Freescale Semiconductor
Bus performance of the operations is as follows:
• Zero wait state (single bus cycle) for each read/write to the CRC_CFG and CRC_INP registers
• Zero wait state (single bus cycle) for each write operation to the CRC_ CSTAT register
• Double wait state (3 bus cycles) for each read operation to the CRC_ CSTAT or CRC_OUTP
registers immediately following (next clock cycle) a write operation to the CRC_CSTAT,
CRC_INP or CRC_CFG registers belonging to the same context. In all the other cases no wait
states are inserted.
The following will result in transfer errors:
• Unaligned reads or writes
• Any attempt to read or write an address that is assigned to the CRC module but not actually mapped
to a register.
29.3 Calculating a CRC checksum
The MPC5644A CRC module has three independent sets of CRC engines and registers, each set called a
context. Each context supports a single data stream, structured as a sequence of bytes, half-words or words,
written to its input register. Since the context operate independently, the CRC module can process up to
three data streams concurrently.
Figure 29-1 illustrates the steps to calculating a CRC checksum (also called a signature) for a data stream:
1. Configure the context to be used.
2. Write a seed value into the CRC Current Status Register (CRC_CSTAT).
3. Write the data to the CRC Input Register (CRC_INP), until the end of the data to be checked.
4. Retrieve the calculated checksum from the CRC Output Register (CRC_OUTP) and verify the
checksum against a stored value.
2. Byte operations must be aligned to 8-bit boundaries, i.e., bits 0–7, bits 8–15, bits 16–23, or bits 24–31. Any unaligned operation
results in a bus error.