FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
1409
BOFFMSK
Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
1: Bus Off interrupt enabled
0: Bus Off interrupt disabled
ERRMSK
Error Mask
This bit provides a mask for the Error Interrupt.
1: Error interrupt enabled
0: Error interrupt disabled
CLKSRC
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral
clock (driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the
prescaler to generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit
should only be changed while the module is in Disable Mode. See
for more information.
1: The CAN engine clock source is the bus clock
0: The CAN engine clock source is the oscillator clock
TWRNMSK
Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRNINT flag in the
Error and Status Register. This bit has no effect if MCR[WRNEN] is negated and it is read as zero
when MCR[WRNEN] is negated.
1: Tx Warning Interrupt enabled
0: Tx Warning Interrupt disabled
RWRNMSK
Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the
Error and Status Register. This bit has no effect if MCR[WRNEN] is negated and it is read as zero
when MCR[WRNEN] is negated.
1: Rx Warning Interrupt enabled
0: Rx Warning Interrupt disabled
LPB
Loop Back
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an
internal loop back that can be used for self test operation. The bit stream output of the transmitter
is fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output
goes to the recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting,
and treats its own transmitted message as a message received from a remote node. In this mode,
FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating
an internal acknowledge bit to ensure proper reception of its own message. Both transmit and
receive interrupts are generated.
1: Loop Back enabled
0: Loop Back disabled
Table 32-10. CR Register field descriptions
Field
Description
Summary of Contents for MPC5644A
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