NXP Semiconductors MPC5644A, Reference Manual, Page: 755 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 755
• Increased linear code memory, shared by two eTPU engines, configurable up to 16K positions (64
Kbytes)
• Increased Parameter RAM address range (8 Kbytes each engine) and width (32 bits per parameter).
The Parameter RAM can be dynamically allocated to support variable number of parameters for
each channel. Each channel can have access to at least 256 parameters.
• The Parameter RAM is fully shared by two eTPU engines (SPRAM), supporting direct
inter-engine communication with the help of hardware semaphores.
• Enhanced arithmetic operations, including add/subtract with carry, absolute value, multiple shift
and rotate, conditional execution with variable operand widths
• Enhanced logic operations, including bitwise operations (and, or, xor) and bit manipulation, with
conditional execution. Support for read-modify-write of any bit in the SPRAM.
• Hardware for Multiply/MAC/Divide, running in parallel to execution of other operations. The
24-bit divide result is available after 13 other unrelated instructions. Multiplication supports any
data width of both operands (8, 16 or 24 bits), signed or unsigned. A 24x24 Multiply/MAC result
is available after four other unrelated instructions. A 24x8 Multiply/MAC result is available after
one other unrelated instruction.
• Supports export/import of time bases from other sources through the real time bus (STAC - Shared
Time and Counter bus). This internal bus is used for sharing real time data between multiple
peripherals.
• Contains angle clock hardware, supported by microcode, which can provide a 24-bit angle bus
instead of time bus. This feature enables the eTPU to run angle based engine control applications.
• More interrupt types. Each eTPU channel can generate a data transfer request interrupt, in addition
to regular interrupts, and one global exception interrupt. Data Transfer requests can be used either
as interrupt sources or DMA requests. This feature takes advantage of DMA peripherals which
offload the Host. Interrupt Overflow status is also provided.
• Improved visibility to the Host (pin states, time bases, serviced channel)
• An edge case of priority inversion on TPU3 Scheduler was resolved.
• Supports channel link requests between eTPU engines
24.2.2.3 eTPU2 enhancements over eTPU
• TCR1, channel logic and digital filters (both channel and TCRCLK) now have an option to run at
divisions of full system clock speed, besides system clock / 2.
• Channels support unordered transitions: transition B can now be detected before transition A.
Related to this enhancement, TDLA and TDLB can now be independently negated by microcode.
• Added a new User Programmable Channel Mode: the blocking, enabling, service request and
capture characteristics of this channel mode can be programmed via microcode.
• Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by
CHAN. They can also be requested simultaneously at the same instruction.
• Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point.
• Channel digital filters can be bypassed.
• Scheduler priority-passing mechanism can now be disabled.