NXP Semiconductors MPC5644A, Reference Manual, Page: 244 / 1735

Flash memory
MPC5644A Microcontroller Reference Manual, Rev. 6
244 Freescale Semiconductor
Table 12-18. UMISRn field descriptions
Field Description
MS Multiple Input Signature Register bits
The MS bitfields accumulate a signature from an array integrity event. The MISR captures all data fields,
as well as ECC fields, and the read transfer error signal. The MISR can be seeded to any value by writing
the UMISR registers.
The UMISR provides a means to calculate an MISR during Array Integrity operations.
The MISR can be represented by the following polynomial:
x
145
+ x
6
+ x
5
+ x
1
+ 1
The MISR is calculated by taking the previous MISR value and then “exclusive ORing” the new data. In
addition the most significant bit (in this case it is MISR[144]), is then “exclusive ORed” into input of
MISR[6], MISR[5], MISR[1], and MISR[0]. The result of the “exclusive OR” is shifted left on each read.
The MISR is used in Array Integrity operations.
If during address sequencing, reads extend into an invalid address location (i.e., greater than the
maximum address for a given array size) or locked/unselected blocks, reads are still executed to the array,
but the results from the array read are not deterministic. In this instance, the signature is not recalculated
and the previous value is retained.
After running the user-test-mode margin read (also referenced as factory margin read) sequence on the
C90fl flash module, the MISR registers cannot be written such that the next user-test-mode margin read
sequence cannot seed the MISRs as desired. This will cause the generated MISRs to be unexpected for
the next user margin read sequences, in case customers want to run the user margin read more than once.
To be able to write the MISR registers:
1) Assert reset after each user margin read sequence so that MISRs can be written again.
2) Do a dummy program to a locked block after user margin read.