NXP Semiconductors MPC5644A, Reference Manual, Page: 1141 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1141
25.6.8
EQADC
DMA/Interrupt request
Table 25-72 lists methods to generate interrupt requests in the EQADC queuing control and triggering
control. The DMA/interrupt request select bits and the DMA/interrupt enable bits are described in
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) , and the interrupt flag
bits are described in Section 25.5.2.9, EQADC FIFO and Interrupt Status Registers (EQADC_FISR) .
Table 25-84 depicts all interrupts and DMA requests generated by the EQADC.
Table 25-73 describes a list of methods to generate DMA requests in the EQADC.
Table 25-72. EQADC FIFO Interrupt Summary
1
1
For details refer to Section 25.5.2.9, EQADC FIFO and Interrupt Status Registers (EQADC_FISR) , and
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) .
Interrupt Condition Clearing Mechanism
Non Coherency
Interrupt
NCIEx = 1
NCFx = 1
Clear NCFx bit by writing a “1” to the bit.
Result FIFO Overflow
Interrupt
2
2
Apart from generating an independent interrupt request for when a RFIFO Overflow Interrupt, a CFIFO
Underflow Interrupt, and a CFIFO Trigger Overrun Interrupt occurs, the EQADC also provides a combined
interrupt request at which these requests from ALL CFIFOs are ORed. Refer to
Figure 25-84 for details.
RFOIEx = 1
RFOFx = 1
Clear RFOFx bit by writing a “1” to the bit.
Command FIFO
Underflow Interrupt
2
CFUIEx = 1
CFUFx = 1
Clear CFUFx bit by writing a “1” to the bit.
Result FIFO Drain
Interrupt
RFDEx = 1
RFDSx = 0
RFDFx = 1 Clear RFDFx bit by writing a “1” to the bit.
Command FIFO
Fill Interrupt
CFFEx = 1
CFFSx = 0
CFFFx = 1
Clear CFFFx bit by writing a “1” to the bit.
End of Queue Interrupt EOQIEx = 1
EOQFx = 1
Clear EOQFx bit by writing a “1” to the bit.
Pause Interrupt PIEx = 1
PFx =1
Clear PFx bit by writing a “1” to the bit.
Trigger Overrun
Interrupt
2
TORIEx = 1
TORFx =1
Clear TORFx bit by writing a “1” to the bit.
Table 25-73.
EQADC
FIFO DMA Summary
1
1
For details refer to Section 25.5.2.9, EQADC FIFO and Interrupt Status Registers (EQADC_FISR) , and
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) .
DMA Request Condition Clearing Mechanism
Result FIFO Drain
DMA Request
RFDEx = 1
RFDSx = 1
RFDFx = 1 The
EQADC
automatically clears the RFDFx when RFIFOx
becomes empty. Writing “1” to the RFDFx bit is not allowed.
Command FIFO Fill
DMA Request
CFFEx = 1
CFFSx = 1
CFFFx = 1 The
EQADC
automatically clears the CFFFx when CFIFOx
becomes full. Writing “1” to the CFFFx bit is not allowed.