NXP Semiconductors MPC5644A, Reference Manual, Page: 1036 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1036 Freescale Semiconductor
2
PFx
Pause Flag x
PF behavior changes according to the CFIFO trigger mode. In edge trigger mode, PFx is set
when the EQADC completes the transfer of an entry with an asserted Pause bit from
CFIFOx. In level trigger mode, when CFIFOx is in TRIGGERED status, PFx is set when
CFIFO status changes from TRIGGERED due to the detection of a closed gate. An interrupt
routine, generated due to the asserted PF, can be used to verify if a complete scan of the
CQueue was performed. If a closed gate is detected while no command transfers are taking
place, it will have immediate effect on the CFIFO status. If a closed gate is detected while a
command transfer to an on-chip CBuffer is taking place, it will only affect the CFIFO status
when the transfer completes. If a closed gate is detected during the serial transmission of a
command to the external device, it will have no effect on the CFIFO status until the
transmission completes. The transfer of entries bound for the on-chip ADCs is considered
completed when they are stored in the appropriate CBuffer. The transfer of entries bound for
the external device is considered completed when the serial transmission of the entry is
completed. In software trigger mode, PFx will never become asserted.
If PIE
x in Section 25.5.2.8, EQADC Interrupt and DMA Control Registers (EQADC_IDCR) ,
and PFx are asserted, an interrupt will be generated. Write “1” to clear the PF x . Writing a “0”
has no effect. Refer to Section 25.6.4.7.3, Pause Status , for more information on the Pause
Flag.
1 Entry with asserted PAUSE bit was transferred from CFIFOx (CFIFO in edge trigger
mode), or CFIFO status changes from TRIGGERED due to detection of a closed gate
(CFIFO in level trigger mode).
0 Entry with asserted PAUSE bit was not transferred from CFIFOx (CFIFO in edge trigger
mode), or CFIFO status did not change from TRIGGERED due to detection of a closed
gate (CFIFO in level trigger mode).
Note: In edge trigger mode, an asserted PFx only implies that the EQADC has finished
transferring a command with an asserted PAUSE bit from CFIFOx. It does not imply
that result data for the current command and for all previously transferred commands
has been returned to the appropriate RFIFO.
Note: In software or level trigger mode, when the EQADC completes the transfer of an entry
from CFIFOx with an asserted PAUSE bit, PFx will not be set and transfer of
commands will continue without pausing.
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EOQFx
End of Queue Flag x
EOQFx indicates that an entry with an asserted EOQ bit was transferred from CFIFOx to the
on-chip ADCs or to the external device - see
Section 25.6.2.3, Message Format in EQADC ,
for details about command message formats. When the EQADC completes the transfer of
an entry with an asserted EOQ bit from CFIFOx, EOQFx
will be set. The transfer of entries
bound for the on-chip ADCs is considered completed when they are stored in the appropriate
CBuffer. The transfer of entries bound for the external device is considered completed when
the serial transmission of the entry is completed. If the EOQIEx bit in
Section 25.5.2.8,
EQADC Interrupt and DMA Control Registers (EQADC_IDCR) , and EOQFx are asserted,
an interrupt will be generated. Write “1” to clear the EOQFx bit. Writing a “0” has no effect.
Refer to
Section 25.6.4.7.2, CQueue Completion Status , for more information on the End of
Queue Flag.
1 Entry with asserted EOQ bit was transferred from CFIFOx.
0 Entry with asserted EOQ bit was not transferred from CFIFOx.
Note: An asserted EOQFx only implies that the EQADC has finished transferring a
command with an asserted EOQ bit from CFIFOx. It does not imply that result data for
the current command and for all previously transferred commands has been returned
to the appropriate RFIFO.
Table 25-15.
EQADC
FIFO and Interrupt Status Register x (
EQADC
_FISRx) field description (continued)
Field Description