NXP Semiconductors MPC5644A, Reference Manual, Page: 595 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 595
If an attempt to force a non-correctable inversion (by asserting ECSM_EEGR[FRCNCI] or
ECSM_EEGR[FRC1NCI]) and ECSM_EEGR[ERRBIT] equals 64, then no data inversion will be
generated.
The only allowable values for the four control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in unpredictable operations.
ERRBIT
[6:0]
The vector defines the bit position which is complemented to create the data inversion on the write
operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit
of the ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome
bits can be generated by setting this field to a value greater than the RAM width. For example,
consider a 64-bit RAM implementation and ECC organized on a 32-bit boundary.
The 32-bit ECC approach requires 7 code bits for each 32-bit word. For RAM data width of 64 bits,
the actual SRAM is 2 × (32 bits data + 7 bits for ECC) = 78 bits which is organized as two 39-bit
memory banks, “even” bank and “odd” bank. The following association between the ERRBIT field and
the corrupted memory bit is defined:
if ERRBIT = 0, then RAM[0] of the odd bank is inverted
if ERRBIT = 1, then RAM[1] of the odd bank is inverted
...
if ERRBIT = 31, then RAM[31] of the odd bank is inverted
if ERRBIT = 32, then RAM[0] of the even bank is inverted
if ERRBIT = 33, then RAM[1] of the even bank is inverted
...
if ERRBIT = 63, then RAM[31] of the even bank is inverted
if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted
if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted
...
if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted
if ERRBIT = 71, then ECC Parity[0] of the even bank is inverted
if ERRBIT = 72, then ECC Parity[1] of the even bank is inverted
...
if ERRBIT = 77, then ECC Parity[6] of the even bank is inverted
For ERRBIT values between 78 and 95, no bit position is inverted. To accommodate address bus
inversions, the ERRBIT values start at 96 as defined:
if ERRBIT = 96, then ADDR[0] is inverted
if ERRBIT = 97, then ADDR[1] is inverted
...
if ERRBIT = 114, then ADDR[18] is inverted
if ERRBIT = 115, then ADDR[19] is inverted
For ERRBIT values greater than 115, the address bus inversion has no effect as only the lower 20 bits
are used by the platform RAM controller.
1
This field is writable only in test mode in cut 1.0 devices.
Table 18-8. ECSM_EEGR field description (continued)
Name Description