NXP Semiconductors MPC5644A, Reference Manual, Page: 111 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 111
Figure 5-4. Bypass mode with external reference
5.3.4.3 Normal mode with crystal reference
In the normal mode with crystal reference, the FMPLL receives an input clock frequency from the crystal
oscillator and the pre-divider, and multiplies the frequency to create the FMPLL output clock. The user
must supply a crystal that is within the appropriate frequency range, the crystal manufacturer
recommended external support circuitry, and short signal route from the MCU to the crystal.
In normal mode with crystal reference, the FMPLL can generate a frequency-modulated clock or a
non-modulated clock (locked on a single frequency). The modulation rate, modulation depth, output
divider (RFD) and whether the FMPLL is modulating or not can be programmed by writing to the FMPLL
registers. The system clock divider (SYSDIV) can also be used to further reduce the system clock
frequency in addition to the FMPLL output divider. The system clock divider can be programmed by
writing to SIU_SYSDIV[SYSDIV]. See
Section 16.6.31, System Clock Register (SIU_SYSDIV) for
details.
NOTE
The PLL output frequency (before the system clock divider) must not
exceed the maximum device operating frequency. Therefore, when
operating at the maximum operating frequency, the only division factor
allowed in the system clock divider is divide-by-1.
0
1
0
1
XTAL OSC
FMPLL
XTAL
EXTAL
PLLREF
clkcfg[0]
SYSDIV
/2, /4, /8, /16
bypass_sysdiv
siu_system_div[1:0]
IDF
PD
ODF NDIV Lock
Control & Status Registers
PHI
CLKIN
Clock Quality Monitor
(CQM)
loss of
VCO
loss of
Reference
system
clock
RCOSC