NXP Semiconductors MPC5644A, Reference Manual, Page: 1653 / 1735

Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1653
The LVI monitors can be configured to generate power-on reset by programming the LVRER, LVREH,
LVRE50, LVRE33 and LVREC bits in the MCR register.
The combination of POR and LVI sources within the PMC generates a single power-on reset output signal
which can be distributed throughout the device.
The following sections discuss the various modules and functions that use the POR.
35.4.7.1.1 Clock control
The clock control divides the system clock to generate CLKOUT. Because CLKOUT toggles during
system reset, one of the sources of reset for the dividers is POR.
35.4.7.1.2 SIU
The SIU uses POR in its reset controller state machine, synchronizers and RESET filter, SIU_RSR,
SIU_RCSR, SIU_CCR and an internal register.
Reset controller state machine
Because the reset controller state machine is active during system reset, it is reset with POR.
Synchronizers and Reset filter
Signals affecting the reset controller’s ability to negate system reset need to be synchronized with
synchronizers reset by POR if they are asynchronous or come from clock domains other than the system
clock.
A synchronized and filtered assertion of the RESET pin will hold the device in system reset. The
synchronizers and filter are reset with POR so that RESET appears to be asserted while POR is asserted.
Synchronizers for the watchdog, Nexus, checkstop, and JTAG sources of reset use POR to reset the
synchronizers, but system reset can suffice because those sources are not analyzed until after system reset
negates. The loss of clock source synchronizers also are reset with POR, but since loss of clock results in
loss of lock, which needs and uses POR as reset, system reset can suffice for loss of clock.
The synchronization of WKPCFG and BOOTCFG uses POR. In the case of WKPCFG, the pin is applied
during POR. In the case of BOOTCFG, the pin value is latched before the negation of system reset.
Changes in BOOTCFG have no effect after the negation of system reset.
SIU_RSR
Because POR sets the PORS bit of the SIU_RSR to indicate that POR was the source of reset, the other
source indicators, ERS, LLRS, LCRS, WDRS, CRS, and SSRS, are reset with POR. The WKPCFG and
BOOTCFG bits are reset with POR so that the WKPCFG and BOOTCFG values can be latched at the
negation of system reset. The RGF bit also is reset with POR. The SERF bit is reset with POR, but also is
cleared during system reset. System reset can suffice to reset the SERF bit.