NXP Semiconductors MPC5644A, Reference Manual, Page: 1655 / 1735

Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1655
35.4.7.1.8 Padring
The padring 3-states all of the output pins, including CLKOUT, MCKO, and RSTOUT when the 1.2 V
supply is too low to propagate internal signals, including the POR indication. When the POR indication
can be propagated, the output pins, including CLKOUT, MCKO, and RSTOUT, also are 3-stated during
POR.
During POR, the actual value of the pin cannot be read. Instead, the padring drives an input value. The
actual value during POR is important for only two pins: WKPCFG and PLLREF. The values driven during
POR for all other pins are irrelevant. For those pins, the input value is a 0.
WKPCFG
During POR, the direction of the weak pull is determined by the reset state of the WPS bit in the
SIU_PCRs. For those pins whose WPS reset state is determined by the WKPCFG pin, the value of
WKPCFG is treated as a 1 during POR to be consistent with the default pull up for the WKPCFG pin.
Therefore, those pins whose WPS reset state is determined by WKPCFG will have a pull up during POR.
PLLREF
The PLLREF pins selects whether crystal or external clock is used as clock source in bypass mode, which
is the default mode out of POR. Furthermore, PLLREF selects whether the clock reference is monitored
or not by the Clock Quality Monitor. If the reference is the crystal oscillator, it is monitored. If the
reference is an external clock, it is not monitored.
The PLLREF value during POR is kept at logic level 0 to minimize the probability of a clock glitch in the
more stringent case when PLLREF = 0, therefore the CQM will not monitor the reference clock and the
internal POR will be released as soon as the voltages achieve the LVI thresholds. The clock glitch may
occur when the POR is released near the external clock falling edge. Even if such a glitch happens, it will
be still inside the POR pulse because all synchronous logic that use POR are supposed to synchronize the
POR negation with a double-register.
35.4.7.2 Interrupts
The PMC generates one interrupt request signal for each LVI source: reset-pin-supply (VDDEH6) LVI,
VDDEH1 LVI, 5 V LVI, 3.3 V LVI and 1.2 V LVI. The module also generates combined interrupt request
signal which is asserted whenever any of the three individual interrupt request signals becomes asserted.
35.4.8 Soft-Start (for 1.2 V and 3.3 V regulators)
A soft-start circuit has been implemented for 1.2 V and 3.3 V regulators. This circuit controls the reference
voltage rise time to avoid abrupt ramp-up of these regulators.
35.4.9 ADC test mux
During PMC functional mode it is possible to perform direct measurements through the ADC. PMC
internal voltages are routed to the ADC. Each signal can be measured with ADC running at full speed.
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