NXP Semiconductors MPC5644A, Reference Manual, Page: 574 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
574 Freescale Semiconductor
NOTE
The product of INCSTEP and MODPERIOD cannot be larger than
(2
15

1).
17.5 Functional description
This section explains the FMPLL operation and configuration.
17.5.1 Input clock frequency
The FMPLL is designed to operate over an input clock frequency range as determined by the operating mode. The operating
ranges for each mode are given in
Table 17-11 .
17.5.2 Clock configuration
In legacy mode, the relationship between the output frequency f
sys
and input frequency f
ref
is determined by the PREDIV, MFD
and RFD values programmed in the FMPLL_SYNCR, according to the following equation:
Eqn. 17-1
16 Reserved, should be cleared.
17–31
INCSTEP
Increment step
This 14-bit field is the binary equivalent of the incstep variable derived from the formula:
where MD represents the peak modulation depth in percentage (+/

MD for centered modulation,

2 * MD for modulation below nominal frequency), and EMFD represents the nominal value of the
feedback loop divider.
Table 17-11. Input clock frequency at the predivider input
Mode Input frequency range
Bypass mode with crystal reference
Normal mode with crystal reference 4 MHz – 20/40 MHz
1
1
See Section 17.1, Information specific to this device , for information on crystal frequencies supported.
Bypass mode with external reference
Normal mode with external reference 0 Hz – f
sys
2
2
f
sys
is the system frequency of the MCU. The predivider ratio has to be chosen such that the input to the PLL itself
(after the predivider) does not exceed 16 MHz.
Table 17-10. SYNFMMR field descriptions (continued)
Field Description
incstep round
2
15
1 –
 
MD

EMFD

100 5

modperiod

------------------------------------------------------------ ( )
=
f
sys
f
ref
MFD 4 +
PREDIV 1 +
 
2
RFD

-------------------------------------------------------

=