NXP Semiconductors MPC5644A, Reference Manual, Page: 1536 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1536 Freescale Semiconductor
The start byte address SADR_MBHF[n] of the last message buffer header field that belongs to the receive
FIFO in the FlexRay memory area is determined according to
Equation 33-5 .
SADR_MBHF[n] = (10 * (FR_RFSIR[SIDX] + RFDSR[FIFO_DEPTH])) + SMBA Eqn. 33-5
NOTE
All message buffer header fields assigned to a receive FIFO must be a
contiguous region.
Figure 33-116. Receive FIFO structure
33.6.3.4 Message buffer configuration and control data
This section describes the configuration and control data for each message buffer type.
33.6.3.4.1 Individual message buffer configuration data
Before an individual message buffer can be used for transmission or reception, it must be configured.
There is a set of common configuration parameters that applies to all individual message buffers and a set
of configuration parameters that applies to each message buffer individually.
FR_RFBRIR FR_RFDSR[B] FR_RFSIR[B]
FR_RFARIR FR_RFDSR[A] FR_RFSIR[A]
Frame Header[1] Slot Status[1] Data Field Offset[1]
Receive FIFO Control Register
Message Buffer Header Fields
Message Buffer Data Fields
Frame Header[n] Slot Status[n] Data Field Offset[n]
(min) RFDSR[ENTRY_SIZE] * 2 bytes
RFDSR
[FIFO
_DEP
TH]
+
Frame Header[i] Slot Status[i] Data Field Offset[i]
Frame Data[n]
SADR_MBDF[n]
Frame Data[i]
SADR_MBDF[i]
Frame Data[1]
SADR_MBDF[1]
R
F
DSR[F
IFO_DEP
TH]
SADR_MBHF[n]
SADR_MBHF[i]
SADR_MBHF[1]
Fl
exRay Memory