NXP Semiconductors MPC5644A, Reference Manual, Page: 283 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 283
DATA[0:31] is driven by the EBI when it owns the external bus and it initiates a write transaction to an
external device.DATA[0:31] is driven by an external device during a read transaction from the EBI.For
8-bit and 16-bit transactions, the byte lanes not selected for the transfer do not supply valid data.
DATA[0:31] is driven by the EBI in the address phase with the ADDR value if the Address on Data
multiplexing mode is enabled. See
Section 14.2.3.6, Multiplexed address on data bus mode, for details.
In 16-bit Data Bus Mode, (or for chip-select accesses to a 16-bit port), only DATA[0:15] or DATA[16:31]
are used by the EBI, depending on the setting of the D16_31 bit in the EBI_MCR. See
Section 14.2.3.5,
16-Bit data bus mode .
14.3.2.6 OE — Output Enable
OE is used to indicate when an external memory is permitted to drive back read data. External memories
must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses.
For read cycles, OE is asserted one clock after TS assertion and held until the termination of the transfer.
For write cycles, OE is negated throughout the cycle.
14.3.2.7 RD_WR — Read / Write
RD_WR indicates whether the current transaction is a read access or a write access.
RD_WR is driven in the same clock as the assertion of TS and valid address, and is kept valid until the
cycle is terminated.
14.3.2.8 TA — Transfer Acknowledge
TA is asserted to indicate that the slave has received the data (and completed the access) for a write cycle,
or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the
transaction beats. For write transactions, TA is only asserted once at access completion, even if more than
one write data beat is transferred.
TA is driven by the EBI when the access is controlled by the chip selects (and SETA=0). Otherwise, TA is
driven by the slave device to which the current transaction was addressed.
See Section 14.5.2.8, Termination signals protocol for more details.
14.3.2.9 TS — Transfer Start
TS is asserted by the current bus owner to indicate the start of a transaction on the external bus.
TS is only asserted for the first clock cycle of the transaction, and is negated in the successive clock cycles
until the end of the transaction.
14.3.2.10 WE [0:3] / BE [0:3] — Write/Byte Enables 0-3
Write enables are used to enable program operations to a particular memory. These signals can also be used
as byte enables for read and write operation by setting the WEBS bit in the appropriate Base Register.
WE[0:3]/BE[0:3] are only asserted for chip-select accesses.