NXP Semiconductors MPC5644A, Reference Manual, Page: 115 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 115
The CPU recovers from the halted state when one of the following events happens:
• A valid pending interrupt is detected by the core
• A request to enter debug mode is made by setting the DR bit in the OnCE control register (OCR)
• The processor is in a debug session
• A request to enable the CPU clock input has been made by setting the WKUP bit in the OCR
When one of these events is detected, the CPU asserts an asynchronous output signal that re-enables the
clock to the CPU so that it can exit the stopped state. Typically, the wake-up interrupt request will come
from one of three sources: periodic interval timer (PIT) interrupt, external pin interrupt or CAN wake-up
interrupt.
When the clock to the CPU is gated, the clocks to the platform, the system RAM and the flash memory are
also gated. The platform logic includes the cross-bar, peripheral bridge, DMA and flash memory
controller. Note that the interrupt controller (INTC) and the SIU are not clock gated to allow interrupts to
be used to recover the CPU halt state.
5.3.4.6 Clock dividers
The MCU provides five clock dividers:
• System Clock Divider (SYSDIV)
• External Bus Clock Divider (CLKOUT-DIV)
• Nexus Message Clock Divider (MCKO-DIV)
• Engineering Clock Divider (ENGDIV)
• FlexCAN clock divider (CAN2:1)
5.3.4.6.1 System Clock Divider (SYSDIV)
The system clock divider is placed right at the output of the system clock mux (selection between FMPLL
and the crystal clock) and before the clock is used by any other circuits, including the other clock dividers.
It affects the clock in both normal mode and bypass mode. The system clock divider can be programmed
to divide by 1, 2, 4, 8, or 16 depending on the values of fields BYPASS and SYSCLKDIV in the
SIU_SYSDIV register.
SIU_SYSDIV[BYPASS] determines whether or not the system clock divider is bypassed. The
SIU_SYSDIV[BYPASS] reset value ‘1’ causes the system clock divider to be bypassed and results in a
divide-by-1 reset configuration of the system clock divider. Only if the SIU_SYSDIV[BYPASS] value is
‘0’ can field SIU_SYSDIV[SYSCLKDIV] be programmed to divide by 2, 4, 8, or 16.
5.3.4.6.2 External Bus Clock (CLKOUT)
The external bus clock (CLKOUT) divider can be programmed to divide the system clock by one, two or
four based on the settings of the EBDF field in the SIU external clock control register (SIU_ECCR). The
reset value of SIU_ECCR[EBDF] selects a CLKOUT frequency of one half of the system clock frequency.
The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress.