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NXP Semiconductors MPC5644A Reference Manual Download Page 1640

Power Management Controller (PMC)

MPC5644A Microcontroller Reference Manual, Rev. 6

1640

Freescale Semiconductor

 

Table 35-3. MCR field descriptions

Field

Description

0

LVRER

Reset-pin-supply LVI (VDDEH6) LVI reset enable
This bit defines whether an LVI assertion on the VDDEH6 supply will generate system reset or not.
0 No reset—LVI assertion on the supply of the I/O segment that contains the reset pin does not cause 

system reset.

1 Reset—LVI assertion on the supply of the I/O segment that contains the reset pin causes system 

reset.

1

LVREH

VDDEH1 LVI reset enable
This bit defines whether an LVI assertion on the VDDEH1 supply will generate system reset or not.
0 No reset—LVI assertion on the VDDEH supply does not cause system reset.
1 Reset—LVI assertion on the VDDEH supply causes system reset.

2

LVRE50

5 V LVI reset enable
This bit defines whether an LVI assertion on the 5 V supply of the voltage regulator (VDDREG) will 
generate system reset or not.
0 No reset—LVI assertion on the 5 V supply of the voltage regulator does not cause system reset.
1 Reset—LVI assertion on the 5 V supply of the voltage regulator causes system reset.

3

LVRE33

3.3 V LVI reset enable
This bit defines whether an LVI assertion on the 3.3 V supply will generate system reset or not.
0 No reset—LVI assertion on the 3.3 V supply does not cause system reset.
1 Reset—LVI assertion on the 3.3 V supply causes system reset.

4

LVREC

1.2 V LVI reset enable
This bit defines whether an LVI assertion on the 1.2 V supply will generate system reset or not.
0 No reset—LVI assertion on the 1.2 V supply does not cause system reset.
1 Reset—LVI assertion on the 1.2 V supply causes system reset.

5:7

Reserved

8

LVIER

Reset-pin-supply (VDDEH6) LVI enable
This bit enables the generation of the LVI interrupt request when the VDDEH6 LVI falls below the 
corresponding LVI threshold. The LVI interrupt is independent from LVI reset. If both, interrupt and reset, 
are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt.
0 Disabled—LVI interrupt request is disabled.
1 Enabled—LVI interrupt request is enabled.

9

LVIEH

VDDEH1 LVI enable
This bit enables the generation of the LVI interrupt request when the VDDEH1 supply falls below the 
corresponding LVI threshold. The LVI interrupt is independent from LVI reset. If both, interrupt and reset, 
are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt.
0 Disabled—LVI interrupt request is disabled.
1 Enabled—LVI interrupt request is enabled.

10

LVIE50

5 V LVI enable
This bit enables the generation of the LVI interrupt request when the 5 V supply of the voltage regulator 
(VDDREG) falls below the corresponding LVI threshold. The LVI interrupt is independent from LVI reset. 
If both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then 
clear the interrupt.
0 Disabled—LVI interrupt request is disabled.
1 Enabled—LVI interrupt request is enabled.

Summary of Contents for MPC5644A

Page 1: ...MPC5644A Microcontroller Reference Manual Rev 6 Freescale Semiconductor 1 MPC5644A Microcontroller Reference Manual Devices Supported MPC5644A MPC5643A MPC5644ARM Rev 6 16 Jan 2012...

Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...

Page 3: ...38 1 4 10 BAM 39 1 4 11 eMIOS 40 1 4 12 eTPU2 40 1 4 13 Reaction module 42 1 4 14 eQADC 42 1 4 15 DSPI 44 1 4 16 eSCI 45 1 4 17 FlexCAN 46 1 4 18 FlexRay 47 1 4 19 System timers 47 1 4 20 Software wat...

Page 4: ...ers in the SIU 100 4 7 Reset configuration 101 4 7 1 Reset configuration half word RCHW 101 4 7 2 Reset configuration timing 103 4 7 3 Reset weak pull up down configuration 104 Chapter 5 Operating Mod...

Page 5: ...teger unit features 135 7 3 3 Load Store unit features 135 7 3 4 Cache features 135 7 3 5 MMU features 135 7 3 6 e200z4 system bus features 136 7 3 7 Nexus 3 features 136 Chapter 8 Enhanced Direct Mem...

Page 6: ...eatures 205 10 2 PBRIDGE modes of operation 205 10 3 PBRIDGE block diagram 205 10 4 PBRIDGE signal description 206 10 5 PBRIDGE functional description 206 10 5 1 Read cycles 206 10 5 2 Write cycles 20...

Page 7: ...ite RWW 245 12 4 4 UTest Mode 246 12 4 5 Flash Programming 249 12 4 6 Flash Erase 252 12 4 7 Flash shadow block 255 12 4 8 Flash reset 256 12 4 9 DMA requests 256 12 4 10Interrupt requests 256 Chapter...

Page 8: ...4 6 3 Running with asynchronous memories 334 14 6 4 Connecting an mcu to multiple memories 336 14 6 5 EBI operation with reduced Pinout MCUs 337 14 6 6 Summary of Differences from MPC5xx 338 Chapter 1...

Page 9: ...8 DMA Interrupt Request Select Register SIU_DIRSR 395 16 6 9 Overrun Status Register SIU_OSR 396 16 6 10Overrun Request Enable Register SIU_ORER 396 16 6 11IRQ Rising Edge Event Enable Register SIU_IR...

Page 10: ...features 559 17 1 2 Device specific parameters 559 17 2 Introduction 559 17 2 1 Overview 560 17 2 2 Features 560 17 2 3 Modes of operation 561 17 3 External signal description 562 17 3 1 Detailed sig...

Page 11: ...ures 613 20 1 3 Modes of operation 613 20 2 External signal description 613 20 3 Memory map and register definition 613 20 3 1 Memory map 614 20 3 2 Register descriptions 614 20 4 Functional descripti...

Page 12: ...1 Features 689 23 1 2 Modes of operation 689 23 1 3 Block diagram 691 23 2 Signal description 695 23 2 1 REACM_RCHn REACM Channel n Output Pin a b and c 696 23 3 Memory map and register definition 696...

Page 13: ...t 734 23 8 Reset overview 735 23 9 Reaction module interrupts 735 23 9 1 Interrupt sources 736 23 10Use cases 736 23 10 1Advancing modulation phase on a threshold level 742 23 10 2Controlling the loop...

Page 14: ...988 24 7 1 Microcycle and I O timing 988 24 7 2 Initialization code example 992 24 7 3 Predefined channel mode summary 995 24 7 4 MISC algorithm 999 Chapter 25 Enhanced Queued Analog to Digital Conver...

Page 15: ...Result Calibration 1164 25 7 7 EQADC versus QADC 1166 Chapter 26 Decimation Filter 26 1 Information specific to this device 1171 26 1 1 Device specific features 1171 26 1 2 Device specific parameters...

Page 16: ...dure 1224 26 7 Application information 1224 26 7 1 eQADC IP as the PSI master block 1224 26 8 Filter example simulation 1225 26 8 1 Coefficients calculation 1225 26 8 2 Input data calculation 1226 26...

Page 17: ...3 30 4 1 SPI configuration 1254 30 4 2 DSI configuration 1254 30 4 3 CSI configuration 1255 30 5 DSPI frequency support 1255 30 6 Modes of operation 1256 30 6 1 Master mode 1256 30 6 2 Slave mode 1256...

Page 18: ...Us 1333 30 10 6Calculation of FIFO pointer addresses 1334 Chapter 31 Enhanced Serial Communication Interface ESCI 31 1 Introduction 1337 31 1 1 Bibliography 1337 31 1 2 Acronyms and abbreviations 1337...

Page 19: ...process 1422 32 5 4 Receive process 1423 32 5 5 Matching process 1424 32 5 6 Data coherence 1426 32 5 7 Rx FIFO 1428 32 5 8 CAN protocol related features 1430 32 5 9 Modes of operation details 1434 3...

Page 20: ...1594 33 6 15Sync frame filtering 1595 33 6 16Strobe signal support 1596 33 6 17Timer support 1597 33 6 18Slot status monitoring 1598 33 6 19System bus access 1601 33 6 20Interrupt support 1602 33 6 2...

Page 21: ...e Configuration Register MCR 1639 35 3 2 Trimming Register TRIMR 1641 35 3 3 Status Register SR 1644 35 4 Functional description 1647 35 4 1 Bandgap 1647 35 4 2 5 V LVI 1648 35 4 3 3 3 V internal volt...

Page 22: ...2 37 2 Introduction 1673 37 2 1 Overview 1674 37 2 2 Features 1674 37 2 3 Modes of operation 1675 37 3 External signal description 1676 37 3 1 Overview 1676 37 3 2 Detailed signal descriptions 1676 37...

Page 23: ...ductor 23 38 4 Memory map 1696 38 5 Register descriptions 1696 38 5 1 DTS Output Enable Register DTS_ENABLE 1696 38 5 2 DTS Startup Register DTS_STARTUP 1697 38 5 3 DTS Semaphore Register DTS_SEMAPHOR...

Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...

Page 25: ...to develop products with the MPC5644A device It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and basic details of th...

Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...

Page 27: ...KB of instruction cache backed by up to 192 KB on chip SRAM and up to 4 MB of internal flash memory The MPC5644A includes an external bus interface and a calibration bus that is only accessible when...

Page 28: ...Cache 8 KB instruction Non Maskable Interrupt NMI NMI Critical Interrupt MMU 24 entry MPU 16 entry Crossbar switch 5 4 4 4 Core performance 0 150 MHz 0 150 MHz Windowing software watchdog Yes Core Ne...

Page 29: ...h 1 ADC 40 ch ADC_A Yes ADC_B Yes Temp sensor Yes Variable gain amp Yes Decimation filter 2 2 Sensor diagnostics Yes CRC Yes FMPLL Yes VRC Yes Supplies 5 V 3 3 V2 Low power modes Stop Mode Slow Mode P...

Page 30: ...1 3 Device block diagram Figure 1 1 shows a top level block diagram of the MPC5644A 5 Ballmap upwardly compatible with the standardized package ballmap used for various Freescale MPC5xxx family member...

Page 31: ...ory Management Unit MPU Memory Protection Unit PMC Power Management Controller PIT Periodic Interrupt Timer RCOSC low speed RC oscillator REACM Reaction module SIU System Integration Unit SPE Signal P...

Page 32: ...XBAR 24 entry MMU External Bus Interface EBI with slave and master port Fail Safe Protection 16 entry Memory Protection Unit MPU CRC unit with 3 sub modules Junction temperature sensor Interrupts Conf...

Page 33: ...dually programmable as input output or special function Programmable threshold hysteresis Power reduction mode slow stop and stand by modes Flexible supply scheme 5 V single supply with external balla...

Page 34: ...ously requested by more than one master port arbitration logic selects the higher priority master and grants it ownership of the slave port All other masters requesting that slave port are stalled unt...

Page 35: ...4 5 Interrupt controller The INTC interrupt controller provides priority based preemptive scheduling of interrupt requests suitable for statically scheduled hard real time systems For high priority in...

Page 36: ...ons are enforced Two types of access control definitions processor core bus master supports the traditional read write execute permissions with independent definitions for supervisor and user mode acc...

Page 37: ...orts when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions Clock Quality Module Detects the quality of the crystal clock and causes interrupt...

Page 38: ...e non volatile flash memory The non volatile memory NVM can be used to store instructions or data or both The flash module includes a Fetch Accelerator that optimizes the performance of the flash arra...

Page 39: ...Module is a block of read only memory that is programmed once by Freescale and is identical for all MPC5644A MCUs The BAM program is executed every time the MCU is powered on or reset in normal mode...

Page 40: ...ation buffered OPWMB Input period measurement IPM Input pulse width measurement IPWM Double action output compare DAOC Modulus counter buffered MCB Output pulse width and frequency modulation buffered...

Page 41: ...lity in various combinations It includes two 24 bit capture registers two 24 bit match registers 24 bit greater equal and equal only comparators Input and output signal states visible from the host 2...

Page 42: ...p control without CPU assistance It works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop The reaction module has the following...

Page 43: ...r sample rate results to the result FIFOs This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out of band noise while providing a reduced sample rate output to minimiz...

Page 44: ...eues Supports six queues with fixed priority When commands of distinct queues are bound for the same ADC the higher priority queue is always served first Queue_0 can bypass all prioritization bufferin...

Page 45: ...4 16 eSCI Three enhanced serial communications interface eSCI modules provide asynchronous serial communications with peripheral devices and other MCUs and include support to interface to Local Inter...

Page 46: ...Content related addressing 64 message buffers of zero to eight bytes data length Individual Rx Mask Register per message buffer Each message buffer configurable as Rx or Tx all supporting standard and...

Page 47: ...nterrupt Timer PIT Operating system task monitors using the System Timer Module STM 1 4 19 1 Periodic interrupt timer PIT The PIT provides five independent timer channels capable of producing periodic...

Page 48: ...modulus counter clocked by the system clock or the crystal clock that can provide a system reset or interrupt request when the correct software key is not written within the required time window The f...

Page 49: ...re Flash SRAM Peripheral RAM FlexRay CAN eTPU2 Parameter RAM 1 4 23 External bus interface EBI The MPC5644A device features an external bus interface that is available in 324 TEPBGA and calibration pa...

Page 50: ...es for the MPC5644A Power Architecture based MCU in compliance with the IEEE ISTO 5001 2003 and 2010 standards MDO port widths of 4 pins and 12 pins are available in all packages 1 4 27 JTAG The JTAGC...

Page 51: ...ssword that matches the Serial Boot password stored in the internal flash shadow row Censorship is disabled until the next system reset 1 4 28 Development Trigger Semaphore DTS MPC5644A devices includ...

Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...

Page 53: ...LASH Shadow Block FL_B 0x0100_0000 0x1FFF_FFFF 507 MB Emulation Remapping of Flash 0x2000_0000 0x2FFF_FFFF 256 MB External Bus 0x3000_0000 0x3FFF_FFFF 256 MB Calibration Bus 0x4000_0000 0x4000_7FFF 32...

Page 54: ...FFF0_3FFF 16 KB PBRIDGE 0xFFF0_4000 0xFFF0_7FFF 16 KB Crossbar XBAR 0xFFF0_8000 0xFFF0_FFFF 16 KB Reserved 0xFFF1_0000 0xFFF1_3FFF 16 KB MPU 0xFFF1_4000 0xFFF3_7FFF 144 KB Reserved 0xFFF3_8000 0xFFF3_...

Page 55: ...FFF 16 KB FlexCAN_B 0xFFFC_8000 0xFFFC_BFFF 16 KB FlexCAN_C 0xFFFC_C000 0xFFFD_FFFF 80 KB Reserved 0xFFFE_0000 0xFFFE_3FFF 16 KB FlexRay 0xFFFE_4000 0xFFFE_BFFF 32 KB Reserved 0xFFFE_C000 0xFFFE_FFFF...

Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...

Page 57: ...icrocontroller Reference Manual Rev 6 Freescale Semiconductor 57 Chapter 3 Signal Description This chapter describes signals that connect off chip It includes a table of signal properties and the deta...

Page 58: ...143 R4 C14 GPIO 207 ETRIG1 GPIO eQADC Trigger Input G 00 207 I O9 VDDEH7 Slow Up Up 144 P5 B14 GPIO 219 GPIO G 21911 I O VDDEH7 MultiV12 Up Up 122 T6 Reset Configuration RESET External Reset Input P I...

Page 59: ...DDE2 Fast Up Up G1 CS 1 ADDR9 GPIO 1 External chip selects External address bus GPIO P A1 G 01 10 00 1 O I O I O VDDE2 Fast Up Up H1 CS 2 ADDR10 WE 2 BE 2 CAL_WE 2 BE 2 GPIO 2 External chip selects Ex...

Page 60: ...I I O I O VDDE EH Medium Up Up R1 ADDR19 FR_B_TX DATA19 GPIO 15 External address bus Flexray TX data ch B External data bus GPIO P A1 A2 G 001 010 100 000 15 I O O I O I O VDDE EH Medium Up Up R2 ADDR...

Page 61: ...ddress bus External data bus GPIO P A2 G 001 100 000 25 I O I O I O VDDE EH Medium Up Up V1 ADDR30 ADDR68 DATA30 GPIO 26 External address bus External address bus External data bus GPIO P A1 A2 G 001...

Page 62: ...ATA8 ADDR24 GPIO 36 External data bus External address bus GPIO P A1 G 001 010 000 36 I O I O I O VDDE5 Fast Up Up AA7 DATA9 ADDR25 GPIO 37 External data bus External address bus GPIO P A1 G 001 010 0...

Page 63: ...I O VDDE2 Fast Up Up H3 TS ALE GPIO 69 External transfer start Address latch enable GPIO 69 P A1 G 001 010 000 69 I O O I O VDDE2 Fast Up Up K3 TA TS8 GPIO 70 External transfer acknowledge External tr...

Page 64: ...I O VDDE12 Fast CAL_ADDR 20 CAL_DATA 20 Calibration address bus Calibration data bus P A 01 10 345 I O I O VDDE12 Fast CAL_ADDR 21 CAL_DATA 21 Calibration address bus Calibration data bus P A 01 10 3...

Page 65: ...A 3 Calibration data bus P 01 341 I O VDDE12 Fast Up Up CAL_DATA 4 Calibration data bus P 01 341 I O VDDE12 Fast Up Up CAL_DATA 5 Calibration data bus P 01 341 I O VDDE12 Fast Up Up CAL_DATA 6 Calibra...

Page 66: ...e P A 01 10 343 O O VDDE12 Fast CAL_MDO 4 Calibration Nexus Message Data Out P 01 O VDDE12 Fast CAL_MDO 4 CAL_MDO 5 Calibration Nexus Message Data Out P 01 O VDDE12 Fast CAL_MDO 5 CAL_MDO 6 Calibratio...

Page 67: ...a out eTPU A channel output only GPIO P A1 G 01 10 00 75 O O I O VDDEH7 MultiV12 14 126 P10 B19 MDO516 ETPUA4_O8 GPIO 76 Nexus message data out eTPU A channel output only GPIO P A1 G 01 10 00 76 O O I...

Page 68: ...start end out P 01 225 O VDDEH7 MultiV12 14 MSEO 1 117 E16 G22 RDY Nexus ready output P 01 226 O VDDEH7 MultiV12 14 G19 JTAG TCK JTAG test clock input P 01 I VDDEH7 MultiV12 TCK Down TCK Down 128 C16...

Page 69: ...PI D peripheral chip select GPIO P A1 G 01 10 00 88 I O I O VDDEH6 Slow Up Up 98 L14 V20 eSCI SCI_A_TX EMIOS138 GPIO 89 eSCI A TX eMIOS channel GPIO P A1 G 01 10 00 89 O O I O VDDEH6 Medium Up Up 100...

Page 70: ...8 SPI clock pin for DSPI module GPIO A1 G 10 00 98 I O I O VDDEH7 Medium Up Up 141 J15 C15 CS 3 DSPI_D_SIN GPIO 99 DSPI D data input GPIO A1 G 10 00 99 I I O VDDEH7 Medium Up Up 142 H13 B15 DSPI_A_PCS...

Page 71: ...6 Medium Up Up 114 G14 J20 DSPI_B_PCS 4 DSPI_C_SCK GPIO 109 DSPI B peripheral chip select SPI clock pin for DSPI module GPIO P A1 G 01 10 00 109 O I O I O VDDEH6 Medium Up Up 105 H14 K20 DSPI_B_PCS 5...

Page 72: ...le ended Analog Input MUX Address 0 eTPU A channel output only eQADC Serial Data Select P A1 A2 G 001 010 100 000 215 I O O I O VDDEH719 Medium I AN 12 148 A12 C13 AN13 SDO MA1 ETPUA21_O8 SDO Single e...

Page 73: ...ended Analog Input P I VDDA Analog I AN 25 158 B9 A9 AN26 Single ended Analog Input P I VDDA Analog I AN 26 D10 AN27 Single ended Analog Input P I VDDA Analog I AN 27 157 A10 C10 AN28 Single ended Ana...

Page 74: ...Input P I VDDA Analog I REFBYPC 164 B7 B10 eTPU2 TCRCLKA IRQ 7 GPIO 113 eTPU A TCR clock External interrupt request GPIO P A1 G 01 10 00 113 I I I O VDDEH4 Slow Up Up L4 AB12 ETPUA0 ETPUA12_O8 ETPUA19...

Page 75: ...1000 0000 120 I O O O I I O VDDEH4 Medium LVDS WKPCFG WKPCFG 53 L3 AB10 ETPUA7 ETPUA19_O8 DSPI_B_SOUT_L VDS ETPUA6_O8 GPIO 121 eTPU A channel eTPU A channel output only LVDS negative DSPI data out eT...

Page 76: ...1_A GPIO 129 eTPU A channel DSPI B peripheral chip select Reaction channel 1A GPIO P A1 A2 G 001 010 100 000 129 I O O O I O VDDEH1 Medium WKPCFG WKPCFG 40 K2 AA1 ETPUA16 DSPI_D_PCS 1 RCH2_A GPIO 130...

Page 77: ...IO 137 eTPU A channel External interrupt request eTPU A channel output only Flexray ch A TX enable GPIO P A1 A2 A3 G 0001 0010 0100 1000 0000 137 I O I O O I O VDDEH1 Slow WKPCFG WKPCFG 30 H1 M1 ETPUA...

Page 78: ...chip select eTPU A channel output only GPIO P A1 A2 G 001 010 100 000 144 I O O O I O VDDEH1 Medium WKPCFG WKPCFG 22 E1 L4 ETPUA31 DSPI_C_PCS 4 ETPUA13_O8 GPIO 145 eTPU A channel DSPI C peripheral chi...

Page 79: ...TX GPIO 187 eMIOS channel eTPU A channel output only eSCI B TX GPIO P A1 A2 G 001 010 100 000 187 I O O O I O VDDEH4 Slow Up Up 70 P8 W15 EMIOS9 ETPUA9_O8 SCI_B_RX GPIO 188 eMIOS channel eTPU A channe...

Page 80: ...Slow Up Up Y17 EMIOS18 GPIO 197 eMIOS channel GPIO P G 01 00 197 I O I O VDDEH4 Slow Up Up AA17 EMIOS19 GPIO 198 eMIOS channel GPIO P G 01 00 198 I O I O VDDEH4 Slow WKPCFG WKPCFG AB17 EMIOS20 GPIO 19...

Page 81: ...C ground low reference voltage I I VSSA 7 VDDA021 eQADC high reference voltage I 5 V I VDDA0 B11 E3 VSSA022 eQADC ground low reference voltage I I VSSA0 A11 E2 VDDA121 eQADC high reference voltage I 5...

Page 82: ...3 3 V 5 0 V I VDDEH1B25 41 VDDEH1AB25 I O Supply Input I 3 3 V 5 0 V I VDDEH1AB25 K4 K4 VDDEH426 I O Supply Input I 3 3 V 5 0 V I VDDEH426 VDDEH4A26 I O Supply Input I 3 3 V 5 0 V I VDDEH4A26 55 VDDEH...

Page 83: ...22 B2 B21 C3 C20 D4 D17 D19 F21 H21 J9 J10 J11 J12 J13 K9 K10 K11 K12 K13 K14 L9 L10 L11 L12 L13 L14 L21 M11 M12 M13 M14 N9 N10 N12 N13 N14 N21 P9 P10 P12 P13 P14 T19 T21 T22 W4 Y3 Y20 AA21 AB1 AB22 1...

Page 84: ...16 6 15 138 Pad Configuration Register 219 SIU_PCR219 12 Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected otherwise they are high swing 13 On...

Page 85: ...ernal ASIC devices EXTAL Clock Generation Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset PLLREF Clock Generation Reset Co...

Page 86: ...spond to bits 3 31 of the EBI s 32 bit internal address bus ADDR 15 31 can be used as Address and Data signals when configured appropriately for a multiplexed external bus This allows 32 bit data oper...

Page 87: ...read and write operation by setting the WEBS bit in the appropriate EBI Base Register EBI_BRn WE 0 3 are only asserted for write accesses BE 0 3 are asserted for both read and write accesses eMIOS 0...

Page 88: ...of RESET to enable or disable the Nexus Debug port After reset the EVTI pin is used to initiate program synchronization messages or generate a breakpoint EVTO Nexus Output that provides timing to a de...

Page 89: ...lied at the assertion of the internal reset signal assertion of RSTOUT and is sampled 4 clock cycles before the negation of the RSTOUT pin The value is used to configure whether the eTPU and eMIOS pin...

Page 90: ...r 10 clock cycles Assertion of the RESET pin while the device is in reset causes the reset cycle to start over The RESET pin has a glitch detector which detects spikes greater than two clock cycles in...

Page 91: ...23 ADDR24 ADDR25 ADDR26 ADDR27 ADDR28 ADDR29 ADDR30 ADDR31 VDDEH1 3 3 V 5 0 V ETPUA10 ETPUA11 ETPUA12 ETPUA13 ETPUA14 ETPUA15 ETPUA16 ETPUA17 ETPUA18 ETPUA19 ETPUA20 ETPUA21 ETPUA22 ETPUA23 ETPUA24 ET...

Page 92: ...AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 VRH VRL REFBYBC VRC331 3 3 V MCKO MDO0 MDO1 MDO2 MDO3 Other Power Segments VDDREG 5 V VRCCTL VDDPLL 1 2 V VSTBY 0...

Page 93: ...sources and upon detection of a reset event resets internal logic and controls the assertion of the RSTOUT pin The Software External Reset only causes the RSTOUT pin to be asserted for a number of clo...

Page 94: ...s based on the value on the BOOTCFG 0 1 pins See the BAM chapter s functional description for details on the BAM program operation and branch location to application software 4 3 Reset pins 4 3 1 RESE...

Page 95: ...5 Reset source descriptions For the following reset source descriptions refer to the reset flow diagrams in Figure 4 1 and Figure 4 2 Figure 4 1 shows the reset flow for assertion of the RESET pin Fig...

Page 96: ...e Manual Rev 6 96 Freescale Semiconductor Figure 4 1 External reset flow diagram Asserted F T RESET F T Asserted RESET Asserted RESET A Wait 2 Clock Cycles Set Latch Wait 8 Clock Set RGF Bit To entry...

Page 97: ...eset F T F T Clock Cycles Clock Cycles F T Latch WKPCFG Pin Latch PLLREF and BOOTCFG 0 1 Reset Request RSTOUT Negate Internal Resets and Wait CNT1 Wait 4 Clock Cycles Wait CNT1 Apply WKPCFG Pin RSTOUT...

Page 98: ...is external PLLREF 0 the clock is released to the system immediately When the clock is stable and released to the chip the reset controller counts a predetermined number of clock cycles refer to Secti...

Page 99: ...platform watchdog A Core Watchdog Timer Reset occurs when the e200z4 core watchdog timer is enabled the e200z4 core watchdog is counting core clocks which is different than the peripheral platform cl...

Page 100: ...ection 4 3 2 RSTOUT Once the clock count finishes the WKPCFG and BOOTCFG 0 1 pins are sampled The reset controller then waits four clock cycles before negating RSTOUT and the associated bits fields ar...

Page 101: ...respectively The locations for the RCHW are given in Table 4 4 For internal boot the predefined locations are searched in the order given in the table If a valid RCHW is not found in internal boot mod...

Page 102: ...assing control to the user application code 0 Disable core software watchdog timer 1 Enable core watchdog timer after reset The timeout period is 2 5 217 system clocks PS0 Port size Defines the width...

Page 103: ...e internal reset signal assertion of RSTOUT The values of the WKPCFG and BOOTCFG 0 1 pins are latched four clock cycles before the negation of the RSTOUT pin and stored in the SIU_RSR Figure 4 4 Reset...

Page 104: ...the assertion of the internal reset signal assertion of RSTOUT If the WKPCFG signal is logic high at this time pull up devices will be enabled on the eTPU and eMIOS pins If the WKPCFG signal is logic...

Page 105: ...enced as Halt State in Chapter 24 Enhanced Time Processing Unit eTPU2 See the Modes of Operation section of the individual module for a description of how the Debug Mode affects the behavior of the mo...

Page 106: ...ndby RAM Standby mode is entered by removing all power supplies except the one on the VSTBY pin The device is recovered from the standby mode when powered again see Chapter 4 Resets for more informati...

Page 107: ...MHz crystal oscillator with crystal as the reference MHz crystal oscillator bypassed PLL enabled MHz crystal oscillator with crystal as the reference output used as PLL reference frequency MHz crysta...

Page 108: ...IV divider 1 1 2 4 8 16 supported System clock 150 MHz 5 3 3 2 Support for 100 MHz system clock generation The oscillator and PLL support generation of a 100 MHz system clock while using the 40 MHz cr...

Page 109: ...rational mode is bypass with PLL running and the source of the reference clock either the crystal oscillator or external clock is determined by the state of the CLKCFG bit of the FMPLL_ESYNCR1 registe...

Page 110: ...bypassed but the system clock divider SYSDIV can be used to reduce the system clock frequency The system clock divider can be programmed by writing to SIU_ SYSDIV SYSDIV Bypass mode with crystal refer...

Page 111: ...frequency The modulation rate modulation depth output divider RFD and whether the FMPLL is modulating or not can be programmed by writing to the FMPLL registers The system clock divider SYSDIV can als...

Page 112: ...Mode with External Reference 5 3 4 5 Software controlled power management Software controlled power management and clock gating is supported on a peripheral by peripheral basis using a three tiered ap...

Page 113: ...ortion of the modules are clocked by the system clock when they are accessed When the NPC module is disabled by MDIS the MCKO clock is disabled Furthermore the NPC can be configured to disable the MCK...

Page 114: ...e the clocks to the modules and then negate the stop request signal after the required timing has been met 5 3 4 5 3 CPU clock gating The SIU_HLT register has a bit to halt the clock to the CPU but in...

Page 115: ...ider SYSDIV External Bus Clock Divider CLKOUT DIV Nexus Message Clock Divider MCKO DIV Engineering Clock Divider ENGDIV FlexCAN clock divider CAN2 1 5 3 4 6 1 System Clock Divider SYSDIV The system cl...

Page 116: ...gineering clock divider ENGDIV can be programmed to divide system clock This clock is mainly used to clock some ASIC devices integrated on the board There is no timing relation of this clock with resp...

Page 117: ...t should be focused on when optimizing an application for performance by describing the features and recommending settings to be applied It focuses on hardware configurations although certain aspects...

Page 118: ...f branch target addresses Its purpose is to accelerate the execution of software loops with some potential change of flow within the loop body In addition the BTB on the e200z4 has a subroutine call s...

Page 119: ...ion for all branches is enabled 01 Branch Target Buffer allocation is disabled for backward branches 10 Branch Target Buffer allocation is disabled for forward branches 11 Branch Target Buffer allocat...

Page 120: ...ates Following negation of reset and execution of the BAM the instruction and data prefetching is disabled and the number of cycles required to access the internal Flash array is set to its maximum va...

Page 121: ...parking the slave port associated with system RAM on this master generally provides the best overall performance To reconfigure the XBAR as described on the MPC5644A write the following registers 1 X...

Page 122: ...on Cache Lock Bits Flash Clear ICLOA Instruction Cache Lock Overflow Allocate ICEA Instruction Cache Error Action ICORG Cache Organization 0 The cache is organized as 64 sets and 2 ways 1 The cache is...

Page 123: ...t Registers MASx which are special purpose registers to facilitate reading writing and searching the Translation Lookaside Buffer TLB entries These MAS registers are software managed by tlbre tlbwe tl...

Page 124: ...ion profile feedback to make the desired trade offs between enhanced performance and minimized code size The data in Figure 6 4 shows the effects of compiler optimization on a simple application In th...

Page 125: ...s on Small Data Areas 6 4 2 Signal processing extension To further optimize time critical functions the Signal Processing Extension Auxiliary Processing Unit SPE APU may be used The SPE APU provides a...

Page 126: ...length encoding APU providing improved code density The VLE APU can be viewed as a supplement to the existing Power Architecture instruction set that can be conditionally applied to a portion of or an...

Page 127: ...and compiler setup is only one part of optimizing an entire application Correct use of the peripherals can also dramatically improve overall system performance In particular use of the interrupt contr...

Page 128: ...locate buffers to data and or instructions Fine tune for specific applications Crossbar Switch Park slave SRAM on master port with XBAR_SGPCR2 Set Flash slave port to highest priority with XBAR_MPR0 F...

Page 129: ...no core overhead Shift loading from the CPU to the eTPU2 whenever possible The eTPU2 can provide effective CPU off loading for time and angle based operations The eTPU2 can trigger the ADC directly wi...

Page 130: ...Device Performance Optimization MPC5644A Microcontroller Reference Manual Rev 6 130 Freescale Semiconductor...

Page 131: ...g Extension SPE APU is provided to support real time SIMD fixed point and single precision embedded numerics operations using the general purpose registers All arithmetic instructions that execute in...

Page 132: ...d point operations using the 64 bit General Purpose Register file Embedded Floating Point EFP2 APU supporting scalar and vector SIMD single precision floating point operations using the 64 bit General...

Page 133: ...as optional byte reversal of data These instructions can be pipelined to allow effective single cycle throughput Load and store multiple word instructions allow low overhead context save and restore...

Page 134: ...Branch unit with dedicated branch address adder and branch lookahead logic BTB supporting single cycle execution of successfully predicted branches CPU CONTROL LOGIC LOAD DATA MEMORY MANAGEMENT UNIT A...

Page 135: ...unit supports load store and the load multiple store multiple instructions 32 bit effective address adder for data memory address calculations Pipelined operation supports throughput of one load or s...

Page 136: ...etween the discontinuities Thus static code may be traced Data Trace via Data Write Messaging DWM and Data Read Messaging DRM This provides the capability for the development tool to trace reads and o...

Page 137: ...udes a DMA engine that performs source and destination address calculations and the actual data movement operations along with an SRAM based memory containing the transfer control descriptors TCD for...

Page 138: ...s transfers Peripheral paced hardware requests one per channel All three methods require one activation per execution of the minor loop Support for fixed priority and round robin channel arbitration S...

Page 139: ...using If a register only exists in one of the eDMAs the register description will state that The eDMA s programming model is partitioned into two regions the first region defines a number of register...

Page 140: ...nels 31 00 on page 8 162 32 EDMA_BASE 0x0038 EDMA_BASE 0x00FF Reserved EDMA_BASE 0x0100 EDMA_CPR0 eDMA channel 0 priority register on page 8 163 8 EDMA_BASE 0x0101 EDMA_CPR1 eDMA channel 1 priority re...

Page 141: ...annel 29 priority register on page 8 163 8 EDMA_BASE 0x011E EDMA_CPR30 eDMA channel 30 priority register on page 8 163 8 EDMA_BASE 0x011F EDMA_CPR31 eDMA channel 31 priority register on page 8 163 8 E...

Page 142: ...BASE 0x013D EDMA_CPR61 eDMA channel 61 priority register on page 8 163 8 EDMA_BASE 0x013E EDMA_CPR62 eDMA channel 62 priority register on page 8 163 8 EDMA_BASE 0x013F EDMA_CPR63 eDMA channel 63 prior...

Page 143: ...ontrol descriptor 27 on page 8 165 256 EDMA_BASE 0x1380 EDMA_TCD28 eDMA transfer control descriptor 28 on page 8 165 256 EDMA_BASE 0x13A0 EDMA_TCD29 eDMA transfer control descriptor 29 on page 8 165 2...

Page 144: ...ontrol descriptor 57 on page 8 165 256 EDMA_BASE 0x1740 EDMA_TCD58 eDMA transfer control descriptor 58 on page 8 165 256 EDMA_BASE 0x1760 EDMA_TCD59 eDMA transfer control descriptor 59 on page 8 165 2...

Page 145: ...nnel 1 Priority EDMA_CPR1 eDMA Channel 2 Priority EDMA_CPR2 eDMA Channel 3 Priority EDMA_CPR3 0xFFF4_4104 eDMA Channel 4 Priority EDMA_CPR4 eDMA Channel 5 Priority EDMA_CPR5 eDMA Channel 6 Priority ED...

Page 146: ...3 Priority EDMA_CPR43 0xFFF4_410C eDMA Channel 44 Priority EDMA_CPR44 eDMA Channel 45 Priority EDMA_CPR45 eDMA Channel 46 Priority EDMA_CPR46 eDMA Channel 47 Priority EDMA_CPR47 0xFFF4_4110 eDMA Chann...

Page 147: ...PnPRI fields of the eDMA control register EDMA_CR All group priorities must have unique values prior to any channel service requests occur otherwise a configuration error is reported In group round ro...

Page 148: ...ng data transfer in the same fashion as the CX cancel transfer Stop the executing channel and force the minor loop to be finished The cancel takes effect after the last write of the current read write...

Page 149: ...ported when the link is attempted if bit EDMA_TCD CITER E_LINK is not equal to bit EDMA_TCD BITER E_LINK All configuration error CLM Continuous link mode 0 A minor loop channel link made to itself goe...

Page 150: ...op the cancel request is discarded and the channel retires normally The error cancel transfer is the same as a cancel transfer except the DMAES register is updated with the cancelled channel number an...

Page 151: ...group priorities indicating not all group priorities are unique CPE Channel Priority Error 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities wit...

Page 152: ...d in field EDMA_TCD DADDR indicating EDMA_TCD DADDR is inconsistent with EDMA_TCD DSIZE DOE Destination Offset Error 0 No destination offset configuration error 1 The last recorded error was a configu...

Page 153: ...0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERQ47 ERQ46 ERQ45 ERQ44 ERQ43 ERQ42 ERQ41 ERQ40 ERQ39 ERQ38 ERQ37 ERQ36 ERQ35 ERQ34 ERQ33 ERQ32 W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 154: ...flag must be asserted before an error interrupt request for a given channel is asserted Address EDMA_BASE 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EEI63 EEI62 EEI61 EEI60...

Page 155: ...iven channel The data value on a register write causes the corresponding bit in the EDMA_ERQRH or EDMA_ERQRL to be cleared Setting bit 1 CERQ 0 provides a global clear function forcing the entire cont...

Page 156: ...f this register return all zeroes Offset EDMA_BASE 0x0019 Access User write only 0 1 2 3 4 5 6 7 R W NOP CERQ 0 6 Reset 0 0 0 0 0 0 0 0 Figure 8 9 eDMA Clear Enable Request Register EDMA_CERQR Table 8...

Page 157: ...EDMA_CIRQR provides a memory mapped mechanism to clear a given bit in the EDMA_IRQRH or EDMA_IRQRL to disable the interrupt request for a given channel The given value on a register write causes the...

Page 158: ...written as a 32 bit word Reads of this register return all zeroes Offset EDMA_BASE 0X001C Access User write only 0 1 2 3 4 5 6 7 R W NOP CINT 0 6 Reset 0 0 0 0 0 0 0 0 Figure 8 12 eDMA Clear Interrup...

Page 159: ...e DONE bit in the TCD of the given channel The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared Setting bit 1 CDSB 0 provides a global...

Page 160: ...ly affected by writes to this register it is also affected by writes to the EDMA_CIRQR On writes to the EDMA_IRQRH or EDMA_IRQRL a 1 in any bit position clears the corresponding channel s interrupt re...

Page 161: ...ected The contents of this register can also be polled and a non zero value indicates the presence of a channel error regardless of the state of the EDMA_EEIR Bit EDMA_ESR VLD is a logical OR of all b...

Page 162: ...8 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERR47 ERR46 ERR45 ERR44 ERR43 ERR42 ERR41 ERR40 ERR39 ERR38 ERR37 ERR36 ERR35 ERR34 ERR33 ERR32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 18 eDMA Erro...

Page 163: ...HRS63 HRS62 HRS61 HRS60 HRS59 HRS58 HRS57 HRS56 HRS55 HRS54 HRS53 HRS52 HRS51 HRS50 HRS49 HRS48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HRS47 HRS46 H...

Page 164: ...e empted Pre emption is available only when fixed arbitration is selected for both group and channel arbitration modes A channel s ability to pre empt another channel can be disabled by setting EDMA_C...

Page 165: ...rresponding channel number for each priority register that is EDMA_CPR31 GRPPRI 0b01 CHPRI 0 3 Channel n Arbitration Priority Channel priority when fixed priority arbitration is enabled The reset valu...

Page 166: ...10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0000 SADDR 0x0004 SMOD SSIZE DMOD DSIZE SOFF 0x0008 NBYTES1 1 The fields implemented in Word 2 depend on whether EDMA_CR EMLM is set...

Page 167: ...r size to implement post increment addressing with the SMOD function constraining the addresses to a 0 modulo size range 37 39 0x4 5 7 SSIZE 0 2 Source data transfer size 000 8 bit 001 16 bit 010 32 b...

Page 168: ...ration count This value can be applied to restore the source address to the initial value or adjust the address to reference the next data structure 128 159 0x10 0 31 DADDR 0 31 Destination address Me...

Page 169: ...0 then Adjustment value added to the destination address at the completion of the outer major iteration count This value can be applied to restore the destination address to the initial value or adjus...

Page 170: ...0x1C 16 17 BWC 0 1 Bandwidth control This two bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the eDMA In general as the eDMA processes the inner minor...

Page 171: ...rency model this field is forced to zero when written to while the bit EDMA_TCD DONE is set 0 The current channel s TCD is normal format 1 The current channel s TCD specifies a scatter gather format T...

Page 172: ...ptor is read from the local memory and loaded into the registers of the other address path channel x y After the inner minor loop completes execution the address path hardware writes the new values fo...

Page 173: ...where the sizes are not equal multiple access of the smaller size data are required for each reference of the larger size For example if the source size references 16 bit data and the destination is 3...

Page 174: ...h and control sequence through the required source reads and destination writes to perform the actual data movement The source reads are initiated and the fetched data is temporarily stored in the dat...

Page 175: ...l address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from memory usin...

Page 176: ...r each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQRH and or EDMA_ERQRL registers 6 Request channel service by software setting bit EDMA_TCD START or by har...

Page 177: ...king and scatter gather operations if enabled Figure 8 27 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can occur after each minor loo...

Page 178: ...o errors DMA request Minor loop 3 Current major loop iteration count CITER Example memory array DMA request Minor loop 2 DMA request Minor loop 1 Major loop xADDR Starting address xSIZE Size of one da...

Page 179: ...sts have been removed or a higher priority group 1 request comes in In this sequence for item 2 the DMA acknowledge lines assert only if the selected channel is requesting service via the DMA peripher...

Page 180: ...g DSPID_SR_RFDF 17 DSPID SR RFDF DSPID Receive FIFO Drain Flag eSCIA_COMBTX 18 ESCIA SR TDRE ESCIA SR TC ESCIA SR TXRDY eSCIA combined DMA request of the Transmit Data Register Empty Transmit Complete...

Page 181: ...hannel 18 Flag eMIOS_GFR_F19 43 EMIOS GFR F19 eMIOS channel 19 Flag eTPU_CDTRSR_A_DTRS1 2 44 ETPU CDTRSR_A DTRS12 eTPUA Channel 12 Data Transfer Request Status eTPU_CDTRSR_A_DTRS1 3 45 ETPU CDTRSR_A D...

Page 182: ...lects the highest pending request from the next group in the round robin sequence Servicing continues round robin always servicing the highest priority channel in the next group in the sequence or ski...

Page 183: ...e channel priority levels assigned within the group This scenario could cause the same bandwidth consumption problem as indicated in Section 8 5 4 1 Fixed group arbitration fixed channel arbitration b...

Page 184: ...of the minor loop e read_byte 0x1008 read_byte 0x1009 read_byte 0x100A read_byte 0x100B f write_word 0x2008 third iteration of the minor loop g read_byte 0x100C read_byte 0x100D read_byte 0x100E read_...

Page 185: ...ation of the minor loop e read_byte 0x1008 read_byte 0x1009 read_byte 0x100A read_byte 0x100B f write_word 0x2008 third iteration of the minor loop g read_byte 0x100C read_byte 0x100D read_byte 0x100E...

Page 186: ...ting of 0 for this field disables the modulo feature Table 8 23 shows how the transfer addresses are specified based on the setting of the MOD field Here a circular buffer is created where the address...

Page 187: ...1 channel has completed the major loop and is idle For both activation types the major loop complete status is explicitly indicated via bit EDMA_TCD DONE Bit EDMA_TCD START is cleared automatically wh...

Page 188: ...t When the major loop is exhausted only the major loop channel link fields are used to determine if a channel link should be made For example with the initial fields of EDMA_TCD CITER E_LINK 1 EDMA_TC...

Page 189: ...memory controller forces the TCD major e_link bit to zero on any writes to a channel s TCD word7 after that channel s TCD done bit is set indicating the major loop is complete NOTE The user must clea...

Page 190: ...a channel s TCD word7 if that channel s TCD done bit is set indicating the major loop is complete NOTE The user must clear the TCD done bit before writing the TCD major e_link or TCD e_sg bits The TC...

Page 191: ...d the e_sg bit Table 8 27 Coherency model for method 2 Step Action 1 Write 1b to theTCD d_req bit Note Should a dynamic scatter gather attempt fail setting the d_req bit will prevent a future hardware...

Page 192: ...Enhanced Direct Memory Access Controller eDMA MPC5644A Microcontroller Reference Manual Rev 6 192 Freescale Semiconductor...

Page 193: ...ughout the design thus all master and slave ports have the same data bus width The XBAR has five master ports and four slave ports Figure 9 1 shows a block diagram of the XBAR Figure 9 1 XBAR device s...

Page 194: ...ntil the higher priority master completes its transactions The XBAR has a 32 bit internal address bus and a 64 bit internal data bus 9 1 3 Limitations The XBAR routes bus transactions initiated on the...

Page 195: ...ontrol of the slave port until that transfer is completed The XBAR will terminate all master IDLE transfers as opposed to allowing the termination to come from one of the slave busses Additionally whe...

Page 196: ...9 197 XBAR_Base 0x104 XBAR_Base 0x10F Reserved XBAR_Base 0x110 SGPCR1 General Purpose Control Register for Slave port 1 on page 9 199 XBAR_Base 0x114 XBAR_Base 0X1FF Reserved XBAR_Base 0x200 MPR2 Mast...

Page 197: ...ister XBAR_MPRn Table 9 3 XBAR Master Priority Register Field Descriptions Field Description 0 Reserved This bit is reserved for future expansion It is read as zero and should be written with zero for...

Page 198: ...upward compatibility 17 19 Reserved These bits are reserved for future expansion They are read as zero and should be written with zero for upward compatibility 20 Reserved This bit is reserved for fut...

Page 199: ...on the last master to use the slave port or go into a low power park mode which will force all the outputs of the slave port to inactive states when no master is requesting an access The low power pa...

Page 200: ...ead Only This bit is used to force all of a slave port s registers to be read only Once written to 1 it can only be cleared by hardware reset This bit is initialized by hardware reset The reset value...

Page 201: ...ed by hardware reset The reset value is 00 00 When no master is making a request the arbiter will park the slave port on the master port defined by the PARK bit field 01 When no master is making a req...

Page 202: ...transfer or a locked transfer In this case the new requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port If th...

Page 203: ...only for an access request made by another master port to the slave port No other arbitration penalties are incurred All other masters pay a one clock penalty If park on last POL mode is selected then...

Page 204: ...Multi Layer AHB Crossbar Switch XBAR MPC5644A Microcontroller Reference Manual Rev 6 204 Freescale Semiconductor...

Page 205: ...GE Is only meant for slave peripherals Supports 32 bit peripherals byte halfword and word reads and write are supported to each Supports a pair of accesses for 64 bit fetches 10 2 PBRIDGE modes of ope...

Page 206: ...supported 10 5 2 Write cycles Three clock write accesses are possible with the PBRIDGE when the requested access size is 32 bits or smaller and is not misaligned across a 32 bit boundary Misaligned w...

Page 207: ...0x0020 PACR Reserved PACR1 Reserved PACR4 Reserved 0x0024 Reserved PACR14 PACR15 0x0028 PACR16 PACR17 PACR18 Reserved 0x002C Reserved 0x0040 OPACR OPACR0 Reserved OPACR2 OPACR3 Reserved OPACR5 OPACR6...

Page 208: ...ture 0 1 2 3 R 0 MTR MTW MPL W Reset 0 1 1 1 Table 10 3 MPCRn field structure descriptions Subfield Description MTR Master Trusted for Reads This bit determines whether the master is trusted for read...

Page 209: ...level for accesses The MPCRx MPL control bit for the master must be set If not the access is terminated with an error response and no peripheral access is initiated on the IPS bus WP Write Protect Thi...

Page 210: ...sters PACR The lists of off platform peripheral registers and their corresponding modules are listed in Table 10 7 Table 10 7 Off platform Peripheral Access Control Register OPACR fields Field Periphe...

Page 211: ...EBI OPACR 66 Flash module A OPACR 67 Flash module B OPACR 68 SIU OPACR 71 DTS OPACR 72 eMIOS OPACR 79 PMC OPACR 80 eTPU2 OPACR 81 Reaction module OPACR 82 eTPU parameter RAM OPACR 83 eTPU parameter RA...

Page 212: ...Peripheral Bridge PBRIDGE MPC5644A Microcontroller Reference Manual Rev 6 212 Freescale Semiconductor...

Page 213: ...CC 11 3 Modes of operation 11 3 1 Normal Functional mode Allows reads and writes of the SRAM memory arrays 11 3 2 Standby mode Preserves contents of the standby portion of the memory when the 1 2 V VD...

Page 214: ...f an SRAM ECC read write R W operation and ECC calculations are performed during the write portion of a read write R W operation Because the ECC bits can contain random data after the device is powere...

Page 215: ...is a two stage pipelined bus which makes the timing of any access dependent on the access during the previous clock Table 11 2 shows the wait states for accesses current is the access being measured...

Page 216: ...ts a read modify write operation is generated that checks the ECC value upon the read See Section 11 8 SRAm ecc mechanism NOTE You must initialize SRAM even if the application does not use ECC reporti...

Page 217: ...erasing charge from these elements and a means of selectively sensing reading the charge stored in these elements The flash is addressable by word 32 bits and page 128 bits There are two flash array b...

Page 218: ...e addressed through the slave peripheral bus Low address space High address space Mid address space 1 x 256 KB 1 x 256 KB 1 x 256 KB 8 x 16 KB 2 x 64 KB 2 x 128 KB 1 x 256 KB Flash_B array blocks Flas...

Page 219: ...ad buffering and line prefetch support Device flash has 2 sets of 4 line read buffers 1 set for the 128 bit wide low and medium address space and 1 set for the 256 bit wide high address space Flash bu...

Page 220: ...rase suspend program suspend and erase suspended program Automotive flash which meets automotive endurance and reliability requirements Shadow information stored in non volatile shadow block Independe...

Page 221: ...ash A L0 1 128 16 0x0000_4000 L1 128 16 0x0000_8000 L2 128 16 0x0000_C000 L3 128 16 0x0001_0000 L4 2 128 16 0x0001_4000 L5 128 16 0x0001_8000 L6 128 16 0x0001_C000 L7 128 16 0x0002_0000 L8 3 128 64 0x...

Page 222: ...e Table 12 3 Flash configuration register memory map Offset from FLASH_x_ REGS_BASE1 Register Location 0x0000 MCR Module configuration register on page 12 223 0x0004 LMLR Low mid address space block l...

Page 223: ...ge 12 241 0x0048 UMISR0 User Multiple Input Signature Register 0 on page 12 241 0x004C UMISR1 User Multiple Input Signature Register 1 on page 12 241 0x0050 UMISR2 User Multiple Input Signature Regist...

Page 224: ...blocks 128 KB of LAS available and no MAS or HAS available 001 256 KB Only LAS option for this size is LAS 1 and LAS 2 no MAS or HAS available 010 512 KB Any LAS or MAS option is available no HAS avai...

Page 225: ...that all previous reads from the last reset or clearing of SBC did not require a correction Since this bit is an error flag it must be cleared to a 0 by writing a 1 to the register location A write o...

Page 226: ...PGM can be set only under one of the following conditions User mode read ERS is low and UTE is low Erase suspend ERS and ESUS are 1 with EHV low PGM can be cleared by the user only when PSUS and EHV a...

Page 227: ...Enable High Voltage The EHV bit enables the flash module for a high voltage program erase operation EHV is cleared on reset EHV must be set after an interlock write to start a program erase sequence...

Page 228: ...reset value of these registers is determined by Flash values in the shadow block An erased shadow block causes the reset value to be 1 3 EHV 4 ESUS PSUS Offset 0x0004 Access User read write R LME 0 0...

Page 229: ...ister signifies that the corresponding block is available to receive program and erase pulses The block numbering for Mid Address Space starts with MLOCK 0 and continues until all blocks are accounted...

Page 230: ...0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 HBLOCK W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Unimplemented or Reserved Figure 12 5 High Address Space Block Lock Register HLR Table 12 7 HLR field descr...

Page 231: ...LE is to provide a password and if the password matches SLE is set to reflect the status of enabled and is enabled until a reset operation occurs For SLE the password 0xC3C3_3333 must be written to th...

Page 232: ...E is set at the completion of the requested operation or if a high voltage operation is suspended MSEL is also not writable during UTest operations when AIE is high In the event that blocks are not pr...

Page 233: ...0 R 0 0 0 0 0 0 0 0 0 0 HSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 8 High Address Space Block Select Register HSR Table 12 10 HSR field descriptions Field Descrip...

Page 234: ...vent errors take priority over single bit corrections which take priority over state machine errors This is especially valuable in the event of a RWW operation where the read senses an ECC error or si...

Page 235: ...set to 0b111 by hardware reset 000 Accesses may be pipelined back to back 001 Access requests require one additional hold cycle 010 Access requests require two additional hold cycles 110 Access reques...

Page 236: ...eared by hardware reset 0 No prefetching is triggered by an instruction read access 1 Prefetching may be triggered by any instruction read access PFLIM PFLASH Prefetch Limit This field controls the pr...

Page 237: ...ccess Protection Register BIUAPR Table 12 13 BIUAPR field descriptions Field Description MnAP Master n Access Protection These fields are used to control whether read and write accesses to the flash a...

Page 238: ...ers in the PFLASH controller The buffers can be organized as a pool of available resources or with a fixed partition between instruction and data buffers In all cases when a buffer miss occurs it is a...

Page 239: ...set AIE or set EIE will be ignored For UTE the password 0xF9F9_9999 must be written to the UT0 register SCBE Single Bit Correction Enable SBC enables Single Bit Correction results to be observed in M...

Page 240: ...e is proprietary The alternative sequence AIS 1 is just logically sequential It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary...

Page 241: ...ecks of ECC logic by allowing data bits to be input into the ECC logic and then read out by doing array reads or array integrity checks The DAI 31 0 correspond to the 32 Array bits representing Word 0...

Page 242: ...ure Register 0 UMISR0 Offset FLASH_REGS_BASE 0x004C Access User read write R MS 063 048 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R MS 047 032 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Re...

Page 243: ...11 096 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 19 User Multiple Input Signature Register 3 UMISR3 Offset FLASH_REGS_BASE 0x0058 Access User read write R 0 0 0 0 0 0...

Page 244: ...usive OR is shifted left on each read The MISR is used in Array Integrity operations If during address sequencing reads extend into an invalid address location i e greater than the maximum address for...

Page 245: ...done with higher performance This can create a data coherency issue that must be handled with software Data coherency can be an issue after a program erase or shadow row operations In flash user mode...

Page 246: ...is calculated The customer is free to provide any random or non random code and a valid MISR signature is calculated Once the operations is completed the results of the reads can be checking by readi...

Page 247: ...Factory Margin Read must be done following Initial Factory Conditions One Factory Margin Read is allowed per erase Factory Margin Read may be done to selected and unlocked blocks by combining UT0 MRE...

Page 248: ...required 12 4 4 3 ECC Logic Check ECC logic can be checked by providing data to be read in the UT0 DSI UT1 DAI and or UT2 DAI registers Then array reads can be done ensuring expected results The ECC L...

Page 249: ...ddress Space Block Lock Register HLR and Section 12 3 2 4 Secondary Low Mid Address Space Block Lock Register SLMLR for more information 2 Write the first address to be programmed in the flash module...

Page 250: ...rogramming While MCR DONE is low MCR EHV is high and MCR PSUS is low the user may clear MCR EHV resulting in a program abort A program abort forces the module to step 8 of the program sequence An abor...

Page 251: ...er mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM more words Step 8 No Yes Write MCR PGM...

Page 252: ...ted After it is suspended the flash core may be read only Reads to the blocks being programmed erased return indeterminate data The program sequence is resumed by writing a logic 0 to MCR PSUS MCR EHV...

Page 253: ...gnored The user may terminate the erase sequence by clearing MCR ERS before setting MCR EHV An erase operation may be aborted by clearing MCR EHV assuming MCR DONE is low MCR EHV is high and MCR ESUS...

Page 254: ...eted the value of PEAS is returned to its erase value FC reads while MCR ESUS 1 from the blocks being erased return indeterminate data The erase sequence is resumed by writing a logic 0 to MCR ESUS MC...

Page 255: ...ain address space User mode read state Write MCR ERS 1 Select blocks Erase interlock write Step 1 Step 2 Step 3 Write MCR EHV 1 High voltage active Access MCR DONE Step 4 WRITE ESUS 1 Read MCR DONE 1...

Page 256: ...using the LMLR or SLMLR discussed in Section 12 3 2 Register descriptions Programming the shadow row has similar restrictions to programming the array in terms of how ECC is calculated See Section 12...

Page 257: ...d 2 types of access control definitions processor core bus master supports the traditional read write execute permissions with independent definitions for supervisor and user mode accesses the remaini...

Page 258: ...ess Registers are listed in address order identified by complete name and mnemonic and list the type of accesses allowed The MPU registers can be referenced using 32 bit word accesses only Attempted r...

Page 259: ...GD5 MPU region descriptor 5 on page 13 264 0x0460 MPU_RGD6 MPU region descriptor 6 on page 13 264 0x0470 MPU_RGD7 MPU region descriptor 7 on page 13 264 0x0480 MPU_RGD8 MPU region descriptor 8 on page...

Page 260: ...5 on page 13 269 0x0818 MPU_RGDAAC6 MPU RGD alternate access control 6 on page 13 269 0x081C MPU_RGDAAC7 MPU RGD alternate access control 7 on page 13 269 0x0820 MPU_RGDAAC8 MPU RGD alternate access...

Page 261: ...r MPU_CESR Table 13 3 MPU_CESR field descriptions Field Description 0 7 SPERR Slave Port n1 Error where the slave port number matches the bit number Each bit in this read only field represents a flag...

Page 262: ...cifies the number of region descriptors implemented in the MPU The defined encodings include 0000 8 region descriptors 0010 16 region descriptors This field reads as 0b0010 on the MPC5644A 31 VLD Vali...

Page 263: ...W Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EPID EMN EATTR ERW W Reset not implemented Figure 13 3 MPU Error Detail Register Slave Port n MPU_EDRn Table 13 5 MPU_EDRn field descriptions...

Page 264: ...faulting reference This field is used to determine the bus master that generated the access error 28 30 EATTR Error Attributes This 3 bit read only field records attribute information about the fault...

Page 265: ...ally reserved for data movement engines and their capabilities are limited to separate read and write permissions For these fields the bus master number refers to the physical master ID defined in Tab...

Page 266: ...o expected that system software may adjust only the access controls within a region descriptor MPU_RGDn Word2 as different tasks execute an alternate programming view of this 32 bit entity is provided...

Page 267: ...E Bus Master ID 4 eDMA Read Enable If set this flag allows bus master ID 4 to perform read operations If cleared any attempted read by bus master ID 4 terminates with an access error and the read is n...

Page 268: ...ntrols within a region descriptor MPU_RGDn Word2 only as different tasks execute an alternate programming view of this 32 bit entity is provided If only the access controls are being updated this oper...

Page 269: ...er Mask This 8 bit field provides a masking capability so that multiple process identifiers can be included as part of the region hit determination If a bit in the PIDMASK is set the corresponding bit...

Page 270: ...lows bus master ID 4 to perform read operations If cleared any attempted read by bus master ID 4 terminates with an access error and the read is not performed 7 M4WE Bus Master 4 Write Enable If set t...

Page 271: ...ields For XBAR bus masters that do not output a process identifier the MPU forces the PID term to be asserted 13 5 1 2 Access Evaluation Privilege Violation Determination While the access evaluation m...

Page 272: ...ce does not hit in any region descriptor the attempted access is terminated with an error 13 7 Application Information In an application s system interfacing with the MPU can generally be classified i...

Page 273: ...g region descriptors are logically summed together the boolean OR operator In the following example of a dual core system there are four bus masters the two processors CP0 CP1 and two DMA engines eDMA...

Page 274: ...y to the two processor cores and the remaining peripheral region RGD7 accessible to both processors and the traditional eDMA master This example is intended to show one possible application of the cap...

Page 275: ...ctable Programmable timeout period with 8 external bus clock resolution Configurable wait states via chip selects Three chip select Cal_CS 0 Cal_CS 2 3 signals Multiplexed with 2 most significant addr...

Page 276: ...he capability of loading engine calibration data into SRAM instead of flash memory making reprogramming the calibration data considerably faster and avoids the necessity of having to reconfigure pins...

Page 277: ...ntrols External Memory 2 Region 3 Controls External Memory 3 Cal_ADDR 13 30 Cal_DATA 0 31 CLKOUT Cal_WE 2 3 BE 2 3 Cal_TS Cal_WE 0 1 Cal_RD_WR Cal_OE Cal_CS0 Cal_CS3 Cal_CS2 CS0 CS2 CS1 CS3 External M...

Page 278: ...s Four Write Byte Enable WE 0 3 BE 0 3 signals Slower speed clock modes Stop and Module Disable Modes for power savings Optional automatic CLKOUT gating to save power and reduce EMI Misaligned access...

Page 279: ...r speed modes are available for a particular MCU 1 2 1 3 etc 14 2 3 5 16 Bit data bus mode For MCUs that have only 16 data bus signals pinned out or for systems where the use of a different multiplexe...

Page 280: ...ddress lines instead of requiring separate non muxed ADDR 8 15 pins This is relevant primarily for devices that support both 32 bit and 16 bit A D muxed operation so therefore have DATA 0 31 pins pres...

Page 281: ...e optimal 16 bit mux mode as it allows access to FlexRay signals on unused EBI signals Operation also possible with EBI_MCR D16_31 1 using DATA 16 31 signals for EBI and leaving DATA 0 15 balls availa...

Page 282: ...to the input clock of another MCU in multi master configurations 14 3 2 4 CAL_CS 0 3 Calibration chip selects 0 3 CAL_CSx is asserted by the master to indicate that this transaction is targeted for a...

Page 283: ...Read Write RD_WR indicates whether the current transaction is a read access or a write access RD_WR is driven in the same clock as the assertion of TS and valid address and is kept valid until the cy...

Page 284: ...14 3 can be overwritten by device logic so see the device specific documentation for any exceptions to the logic below 14 4 Memory map Register definition Table 14 4 shows the EBI registers Table 14 3...

Page 285: ...nk 0 EBI_BR0 EBI_BASE 0x14 EBI Option Register Bank 0 EBI_OR0 EBI_BASE 0x18 EBI Base Register Bank 1 EBI_BR1 EBI_BASE 0x1C EBI Option Register Bank 1 EBI_OR1 EBI_BASE 0x20 EBI Base Register Bank 2 EBI...

Page 286: ...ccesses 1 Automatic CLKOUT Gating is enabled 0 Automatic CLKOUT Gating is disabled 25 MDIS MDIS Module Disable Mode The MDIS bit controls an internal EBI enable clk signal which can be used if MCU log...

Page 287: ...address driven on the data bus in the address phase of a cycle 1 Address on Data Multiplexing Mode is used for non CS accesses 0 Only Data on data pins for non CS accesses 31 DBM DBM Data Bus Mode Th...

Page 288: ...riting a 0 has no effect This register may not be writable in Module Disable Mode due to the use of power saving clock modes e g a bus error can be generated on a timeout EBI_BASE 0x8 0 1 2 3 4 5 6 7...

Page 289: ...MT BME 0 0 0 0 0 0 0 W RESET 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Unimplemented or Reserved Table 14 7 EBI Bus Monitor Control Register EBI_BMCR Field Descriptions Name Description 16 23 BMT BMT Bus Monito...

Page 290: ...sked address signals among ADDR 0 16 of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master Note An MCU may have some...

Page 291: ...s 1 Only assert BDIP BSCY 1 external cycles before expecting subsequent burst data beats 0 Assert BDIP throughout the burst cycle regardless of wait state configuration 29 SETA SETA Select External Tr...

Page 292: ...sses for this bank This is the default value out of reset or when SETA 1 0 Enable burst accesses for this bank 31 V V Valid bit The user writes this bit to indicate that the contents of this Base Regi...

Page 293: ...0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 14 9 EBI Option Registers EBI_OR0 EBI_OR3 EBI_CAL_OR0 3 Field Descriptions Name Description 0 16 AM AM Address Mask This field allows masking of...

Page 294: ...ngth in clocks1 This field determines the number of wait states external cycles inserted in all burst beats except the first when the memory controller starts handling the external memory access and t...

Page 295: ...th Support for Various Memory Types The EBI contains a memory controller that supports a variety of memory types including synchronous burst mode flash and SRAM and asynchronous legacy flash and SRAM...

Page 296: ...sters EBI_OR0 EBI_OR3 EBI_CAL_OR0 3 for a full description of all chip select attributes When no match is found on any of the chip select banks the default transfer attributes shown in Table 14 10 are...

Page 297: ...size See Section 14 5 2 6 Small accesses Small port size and short burst length for more detail on these cases 14 5 1 5 Bus Monitor When enabled via the BME bit in the EBI_BMCR the bus monitor detects...

Page 298: ...bits of the data bus DATA 0 7 contain valid data during a write read cycle The upper middle Write Byte Enable WE1 BE1 indicates that the upper middle eight bits of the data bus DATA 8 15 contain vali...

Page 299: ...s feature is disabled out of reset and can be enabled or disabled by the ACGE bit in the EBI_MCR NOTE This feature must be disabled for multi master systems In those cases one master is getting its cl...

Page 300: ...erns multi master or master slave operation between an eSys MCU and MPC5xx is not guaranteed 14 5 2 External bus operations The following sections provide a functional description of the external bus...

Page 301: ...ter must start driving write data one cycle after the address transfer cycle The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of CLKOUT To facilit...

Page 302: ...escale Semiconductor Figure 14 9 Basic Flow Diagram of a Single Beat Read Cycle MASTER EBI SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer a...

Page 303: ...ductor 303 Figure 14 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States Figure 14 11 Single Beat 32 bit Read Cycle CS Access One Wait State DATA is valid CLKOUT ADDR 3 31 TS TA RD_WR BDIP OE...

Page 304: ...t States 14 5 2 4 2 Single beat write flow The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams DATA is valid The EBI drives address and control signa...

Page 305: ...r 305 Figure 14 13 Basic Flow Diagram of a Single Beat Write Cycle MASTER SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA sto...

Page 306: ...uctor Figure 14 14 Single Beat 32 bit Write Cycle CS Access Zero Wait States Figure 14 15 Single Beat 32 bit Write Cycle CS Access One Wait State DATA is valid CLKOUT ADDR 3 31 TS TA RD_WR BDIP CS n D...

Page 307: ...lect See Figure 14 20 and Figure 14 21 Besides this dead cycle in most cases back to back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams an...

Page 308: ...onductor Figure 14 17 Back to Back 32 bit Reads to the Same CS Bank Figure 14 18 Back to Back 32 bit Reads to Different CS Banks DATA is valid DATA is valid CLKOUT ADDR 3 31 TS TA RD_WR BDIP OE CS n D...

Page 309: ...erface EBI MPC5644A Microcontroller Reference Manual Rev 6 Freescale Semiconductor 309 Figure 14 19 Write After Read to the Same CS Bank ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid BDIP WE CSx DATA...

Page 310: ...e EBI MPC5644A Microcontroller Reference Manual Rev 6 310 Freescale Semiconductor Figure 14 20 Back to Back 32 bit Writes to the Same CS Bank CLKOUT ADDR 3 31 TS TA RD_WR BDIP WE CS n DATA is valid DA...

Page 311: ...o the Same CS Bank 14 5 2 5 Burst transfer The EBI supports wrapping 32 byte critical doubleword first burst transfers Bursting is supported only for internally requested cache line size 32 byte read...

Page 312: ...d atomic by the EBI so the EBI does not allow other unrelated master accesses or bus arbitration to intervene between the transfers For more details and a timing diagram see Section 14 5 2 6 3 Small a...

Page 313: ...4 22 Basic Flow Diagram of a Burst Read Cycle MASTER SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA next to last data beat y...

Page 314: ...timing on the BDIP signal than the default to run burst cycles Using the default value of TBDIP 0 in the appropriate EBI Base Register results in BDIP being asserted SCY 1 cycles after the address tr...

Page 315: ...25 Burst 32 bit Read Cycle One Wait State between Beats TBDIP 0 When using TBDIP 1 the BDIP behavior changes to toggle between every beat when BSCY is a non zero value Figure 14 26 shows an example of...

Page 316: ...noted that all the transactions initiated to complete the data transfer are considered as an atomic transaction so the EBI does not allow other unrelated master accesses to intervene between the tran...

Page 317: ...bit port requiring two 16 bit external transactions Figure 14 27 Single Beat 32 bit Write Cycle 16 bit Port Size Basic Timing 14 5 2 6 2 Small access example 2 32 byte write with external TA Figure 14...

Page 318: ...case the address for the 2nd 4 word burst access is calculated by adding 0x10 to the lower 5 bits of the 1st address no carry and then masking out the lower 4 bits to fix them at zero Table 14 14 Exam...

Page 319: ...Byte Bursts to 32 bit Port Zero Wait States 14 5 2 6 4 Small access example 4 64 bit read to 16 bit Port Figure 14 30 shows an example of a 64 bit read to a 16 bit port requiring four 16 bit external...

Page 320: ...zes that an internal master can request from the EBI The behavior of the EBI for request sizes not shown below is undefined No error signal is asserted for these erroneous cases Table 14 15 Transactio...

Page 321: ...ting TEA externally and does not initiate the access on the internal bus The EBI requires that the portion of the data bus used for a transfer to from a particular port size be fixed A 32 bit port mus...

Page 322: ...required on the data bus for read cycles The bytes indicated as are not required during that read cycle Table 14 17 lists the patterns of the data transfer for write cycles when accesses are initiate...

Page 323: ...ip select accesses Table 14 16 Data Bus Requirements for Read Cycles Transfer Size Address 32 Bit Port Size 16 Bit Port Size1 A30 A31 D0 D7 D8 D15 D16 D23 D24 D31 D0 D72 D8 D153 Byte 0 0 OP0 OP0 0 1 O...

Page 324: ...on a weak internal pullup to hold TEA negated This allows an external device to assert TEA when it needs to indicate an error External devices must follow the same protocol as the EBI only driving TEA...

Page 325: ...e one 32 bit read or write access thus 32 bit coherent as opposed to two separate 16 bit accesses Asserted X Transfer Error Termination Negated Asserted Normal Transfer Termination 1 Latched version 1...

Page 326: ...system if a non chip select 32 bit access to a 16 bit port is performed Figure 14 34 shows a 32 bit and non chip select in a single master system read from an external master in 16 bit data bus mode...

Page 327: ...o back accesses can switch from one bus to the other as determined by the type of chip select each address matches The timing diagrams and protocol for the calibration bus is identical to the primary...

Page 328: ...is section describes all the misaligned cases supported by the EBI These cases are a subset of the full set of cases allowed by the AMBA AHB V6 specification The EBI works under the assumption that al...

Page 329: ...ster AHB bus uses Little Endian byte ordering EBI flips order internally HSIZE4 4 Internal signal on AHB bus 00 8 bits 01 16 bits 10 32 bits 11 64 bits HSIZE is driven according to the smallest aligne...

Page 330: ...and short burst length Since all transfers are aligned on the external bus normal timing diagrams and protocol apply Table 14 20 Misalignment Cases Supported by a 64 bit AMBA EBI external bus No 1 PS...

Page 331: ...an idle clock cycle 10 0 Word 0x7 0xF 2 AHB transfers 1115 1110 11 000 0001 10 1 1115 1011 11 000 010 0011 0111 12 0 Doubleword 0x4 0xC 2 AHB transfers 1007 0000 000 0000 12 1 1007 110 0011 0011 000 0...

Page 332: ...l timing diagrams in A D multiplexing mode are very similar to other diagrams in this document including support for Burst accesses except for the behavior of the ADDR and DATA busses which can be see...

Page 333: ...nal accesses are being performed such as the following method Copy the code that is doing the register writes plus a return branch to internal SRAM Branch to internal SRAM to run this code ending with...

Page 334: ...riod 15 2 ns Assume the input data spec for the MCU is 4 ns number of wait states access time CLKOUT period 0 or 1 depending on setup time 50 15 2 3 with 4 4 ns remaining so we need at least 3 wait st...

Page 335: ...le Semiconductor 335 Figure 14 41 shows a timing diagram of a write operation to a 16 bit asynchronous memory using 3 wait states Figure 14 40 Read Operation to Asynchronous Memory Three Initial Wait...

Page 336: ...e Operation to Asynchronous Memory Three Initial Wait States 14 6 4 Connecting an mcu to multiple memories The MCU can be connected to more than one memory at a time Figure 14 42 shows an example of h...

Page 337: ...described in this document pinned out for a particular package Some of the most common pins to be removed are DATA 16 31 and arbitration pins BB BG ADDR 3 29 CS0 DATA 0 31 TS OE MCU CS1 CK A 0 21 CE...

Page 338: ...no MCU MCU transfers are possible Non chip select accesses have no way for the EBI to know which cycle to latch the data The EBI has no built in protection to prevent non chip select accesses in this...

Page 339: ...code to determine internal slave instead of straight address decode rationale needed for compatibility with internal bridge address decoding and memory map Removed support for 3 master systems rationa...

Page 340: ...Sys devices s requested customer feature Added support for larger external address bus up to 29 bits rationale support larger external memory sizes Added support for address data multiplexing rational...

Page 341: ...eral interrupts 199 reserved interrupts 8 software interrupts 15 2 Introduction This chapter describes the interrupt controller INTC which schedules interrupt requests IRQs from software and internal...

Page 342: ...g 0 SRAM error correction 1 Flash error correction 1 End of interrupt register Software set clear interrupt registers Flag bits Priority select registers 8 Peripheral interrupt requests1 n1 Priority a...

Page 343: ...d by an address derived from special purpose registers IVPR and IVOR4 The interrupt exception handler reads the INTC_IACKR to determine the vector of the interrupt request source Typical program flow...

Page 344: ...in Figure 15 4 Figure 15 4 Program Flow Hardware Vector Mode The INTC supports a hardware vector mode that reduces the time between assertion of an interrupt and execution of the service routine It a...

Page 345: ...are configurable sources 199 are reserved sources 9 bit unique vector for each interrupt request source in hardware vector mode Each interrupt source can be programmed to one of 16 priorities Preempti...

Page 346: ...n the INTC current priority register INTC_CPR to the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request The INTC_CPR masks any peripheral or software configurable interrup...

Page 347: ...gate if a higher priority interrupt request arrives Even in this case the interrupt vector number does not update to the higher priority request until the lower priority request is acknowledged by the...

Page 348: ...ts Base 0xFFF4_8000 INTC_MCR INTC module configuration register 32 Base 0x0004 Reserved Base 0x0008 INTC_CPR INTC current priority register 32 Base 0x000C Reserved Base 0x0010 INTC_IACKR INTC interrup...

Page 349: ...15 6 5 Priority ceiling protocol Address Base 0x0000 INTC_MCR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20...

Page 350: ...Section 15 2 4 1 Software vector mode for a detailed description of the effect on the interrupt request to the processor The reading also pushes the PRI value in the INTC current priority register INT...

Page 351: ...upt Acknowledge Register INTC_IACKR INTC_MCR VTES 0 Figure 15 10 INTC Interrupt Acknowledge Register INTC_IACKR INTC_MCR VTES 1 Address Base 0x0010 INTC_IACKR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 352: ...peripheral interrupt request Writing a 1 to SETn leaves SETn unchanged at 0 but sets CLRn Writing a 0 to SETn has no effect CLRn is the flag bit Writing a 1 to CLRn clears it Writing a 0 to CLRn has n...

Page 353: ...INTC_PSR8 through INTC_PSR485 respectively Although INTC_PSRn is 8 bits wide you can use a single 16 bit or 32 bit access provided that it does not cross a 32 bit boundary NOTE Do not modify the PRIn...

Page 354: ...from the same module location are ORed together The individual Address Base 0x0010 INTC_IACKR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PRI0 0 0 0 0 PRI1 W RESET 0 0 0 0 0 0 0 0 0 0...

Page 355: ...INTC software settable Clear flag 7 ECC 0x0080 8 Reserved 0x0090 9 ECSM_ESR RNCE ECSM_ESR FNCE ECSM combined interrupt requests Internal SRAM Non Correctable Error and Flash Non Correctable Error eDM...

Page 356: ...NT26 eDMA channel Interrupt 26 0x0260 38 EDMA_IRQRL INT27 eDMA channel Interrupt 27 0x0270 39 EDMA_IRQRL INT28 eDMA channel Interrupt 28 0x0280 40 EDMA_IRQRL INT29 eDMA channel Interrupt 29 0x0290 41...

Page 357: ...eTPU_A 0x0430 67 ETPU_MCR MGEA ETPU_MCR MGEB ETPU_MCR ILFA ETPU_MCR ILFB ETPU_MCR SCMMISF eTPU Global Exception 0x0440 68 ETPU_CISR_A CIS0 eTPU Engine A Channel 0 Interrupt Status 0x0450 69 ETPU_CISR...

Page 358: ...pt Status 0x05C0 92 ETPU_CISR_A CIS24 eTPU Engine A Channel 24 Interrupt Status 0x05D0 93 ETPU_CISR_A CIS25 eTPU Engine A Channel 25 Interrupt Status 0x05E0 94 ETPU_CISR_A CIS26 eTPU Engine A Channel...

Page 359: ...0750 117 EQADC_FISR3 PF eQADC command FIFO 3 Pause Flag 0x0760 118 EQADC_FISR3 EOQF eQADC command FIFO 3 command queue End of Queue Flag 0x0770 119 EQADC_FISR3 CFFF eQADC Command FIFO 3 Fill Flag 0x07...

Page 360: ...s Transmit FIFO Underflow and Receive FIFO Overflow SPI and DSI parity error 0x0890 137 DSPI_CSR EOQF DSPI_C transmit FIFO End of Queue Flag 0x08A0 138 DSPI_CSR TFFF DSPI_C Transmit FIFO Fill Flag 0x0...

Page 361: ...ror 0x0940 148 GIFER LRCE GIFER DRCE FlexRay LRAM corrected error FlexRay DRAM corrected error 0x0950 149 ESCIB_SR TDRE ESCIB_SR TC ESCIB_SR RDRF ESCIB_SR IDLE ESCIB_SR OR ESCIB_SR NF ESCIB_SR FE ESCI...

Page 362: ...x0A80 168 CANA_IFRL BUF13 FLEXCAN_A Buffer 13 Interrupt 0x0A90 169 CANA_IFRL BUF14 FLEXCAN_A Buffer 14 Interrupt 0x0AA0 170 CANA_IFRL BUF15 FLEXCAN_A Buffer 15 Interrupt 0x0AB0 171 CANA_IFRL BUF31I BU...

Page 363: ...98 DECFIL_A_Out Decimation A output Drain 0x0C70 199 DECFIL_A_Err Decimation A Error 0x0C80 200 STM0 STM 0 0x0C90 201 STM1_or_STM2_or_STM3 STM 1 3 eMIOS 0x0CA0 202 EMIOS_GFR F16 eMIOS channel 16 Flag...

Page 364: ...28 EDMA_IRQRH INT49 eDMA channel Interrupt 49 0x0E50 229 EDMA_IRQRH INT50 eDMA channel Interrupt 50 0x0E60 230 EDMA_IRQRH INT51 eDMA channel Interrupt 51 0x0E70 231 EDMA_IRQRH INT52 eDMA channel Inter...

Page 365: ...2 CANB_IFRL BUF9 FLEXCAN_B Buffer 9 Interrupt 0x1250 293 CANB_IFRL BUF10 FLEXCAN_B Buffer 10 Interrupt 0x1260 294 CANB_IFRL BUF11 FLEXCAN_B Buffer 11 Interrupt 0x1270 295 CANB_IFRL BUF12 FLEXCAN_B Buf...

Page 366: ...1 0x1670 359 STM2 STM 2 0x1680 360 STM3 STM 3 0x1690 361 365 REACM_GE REACM 0 REACM 1 REACM 2 REACM 3 Reaction Channel Global Error Reaction Channel 0 3 Interrupt 0x16E0 366 DECFIL_B_In Decimation B...

Page 367: ..._SR NF ESCIC_SR FE ESCIC_SR PF ESCIC_SR BERR ESCIC_SR RXRDY ESCIC_SR TXRDY ESCIC_SR LWAKE ESCIC_SR STO ESCIC_SR PBERR ESCIC_SR CERR ESCIC_SR CKERR ESCIC_SR FRC ESCIC_SR OVFL Combined Interrupt Request...

Page 368: ...lowing Writing a 1 to SETn leaves SETn unchanged at 0 but sets the flag bit CLRn bit Writing a 0 to SETn has no effect Writing a 1 to CLRn clears the flag CLRn bit Writing a 0 to CLRn has no effect If...

Page 369: ...unique 9 bit vector for the asserted interrupt request from the request selector submodule 15 5 2 1 4 Priority comparator submodule The priority comparator submodule compares the highest priority outp...

Page 370: ...ter INTC_IACKR is updated with the preempting interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the interrupt r...

Page 371: ...pdated with the preempting peripheral or software configurable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next tim...

Page 372: ...al and software configurable interrupt requests to generate an interrupt request to the processor is interrupt_request_initialization configure VTES and HVEN in INTC_MCR configure VTBA in INTC_IACKR r...

Page 373: ...R address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition of interrupts stw r4 INTC_EOIR l r3 store to INTC_EOIR informing INTC to lower priority code to restore SRR0 and...

Page 374: ...typically execute with PRI in INTC current priority register INTC_CPR having a value of 0 The RTOS execute the tasks according to whatever priority scheme that it has but that priority scheme is indep...

Page 375: ...iority Table 15 9 Order of ISR Execution Example Step Step Description Code Executing At End of Step PRI in INTC_CPR at End of Step RTOS ISR1081 1 ISR108 executes for peripheral interrupt request 100...

Page 376: ...ing the PCP instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked For example while ISR3 can...

Page 377: ...lines that share a resource They do not need to use the PCP to access the shared resource 15 6 7 Software configurable interrupt requests The software configurable interrupt requests can be used in tw...

Page 378: ...processor after accessing the block of data clears the corresponding CLRn bit and then writes 1 to a SETn bit on the first processor informing it that it now can access the block of data 15 6 8 Loweri...

Page 379: ...TC end of interrupt register INTC_EOIR as the clearing of the flag bit that caused the present ISR to be executed Refer to Section 15 5 3 1 2 End of interrupt exception handler for more information A...

Page 380: ...the preempting interrupt request If the processor recognition of interrupts is disabled during the LIFO restoration interrupt requests to the processor can go undetected However since the peripheral...

Page 381: ...y the core through the peripheral bus 16 2 Features System configuration MCU reset configuration via external pins Pad configuration control System reset monitoring and generation Power on reset suppo...

Page 382: ...em configuration the reset controller and GPIO 16 3 2 Debug mode SIU operation in debug mode is identical to operation in normal mode 16 4 Block diagram Figure 16 1 is a block diagram of the SIU The s...

Page 383: ...ists the external pins used by the SIU Reset Controller RESET SIU Registers Detection GPIO RSTOUT Pad Configuration Power on Reset Peripheral I O Channels Pad Interface Pad Ring Config Reset Edge Exte...

Page 384: ...Configuration Input Down BOOTCFG1 Input Slow Boot Configuration Input Down WKPCFG_ NMI_ GPIO 213 Input Input I O Slow Weak Pull Configuration Pin Non Maskable Interrupt General Purpose I O Up Up Down...

Page 385: ...7B Pad Configuration Register 0 SIU_PCR0 Pad Configuration Register 413 SIU_PCR413 1 16 on page 16 400 SIU_BASE 0x37C SIU_BASE 0x5FF Reserved SIU_BASE 0x600 SIU_BASE 0x79D GPIO Pin Data Output Registe...

Page 386: ...16 543 SIU_BASE 0x990 Compare B High Register SIU_CBRH 32 on page 16 544 SIU_BASE 0x994 Compare B Low Register SIU_CBRL 32 on page 16 544 SIU_BASE 0x998 Reserved SIU_BASE 0x9A0 System Clock Register S...

Page 387: ...DR2 field description Bit Name Description 0 S_F Identifies the manufacturer 0 FSL 1 4 FLASH_SIZE_1 Define major Flash memory size see Table 16 4 for details 5 8 FLASH_SIZE_2 Define Flash memory size...

Page 388: ...ber and the package ID of the device Table 16 4 Flash memory size FLASH_SIZE_1 field Size 0h 16 KB 1h 32 KB 2h 64 KB 3h 128 KB 4h 256 KB 5h 512 KB 6h 1024 KB 7h 2048 KB n 24 n KB Table 16 5 Flash memo...

Page 389: ...NUM 0 15 Device part number is one of following 0x5644 4 MB flash memory 0x5643 3 MB flash memory 0x5647 2 5 MB flash memory 0x5642 2 MB flash memory Please see Table 16 7 for details on memory size 1...

Page 390: ...ll registers named Mode 1 are implemented Figure 16 4 Reset Status Register SIU_RSR 3h 320 KB 384 KB 1024 KB 4h 512 KB 1 5 MB 5h 768 KB 2 MB 6h 1024 KB 3 MB 7h 1 5 MB 4 MB 8h 2 MB 6 MB 9h 3 MB 8 MB SI...

Page 391: ...g Timer Debug Reset Status 1 A Watchdog Timer or Debug Reset has occurred 0 No Watchdog Timer or Debug Reset has occurred 5 Reserved 6 SWTRS Software Watchdog Timer Reset Status 1 An enabled SWT Reset...

Page 392: ...M program to determine the location of the Reset Configuration Word See Table 4 4 in Section 4 7 1 1 RCHW overview for a translation of the Reset Configuration Half Word location from the BOOTCFG fiel...

Page 393: ...Reset Writing a one to this bit causes a Software External Reset The RSTOUT pin is asserted for the predetermined number of clock cycles refer to Section 4 3 2 RSTOUT but the MCU is not reset The bit...

Page 394: ...Software Watch Dog Timer Interrupt Flag from platform This bit is set when a SWT interrupt occurs on the platform 1 An SWT event has occurred 0 No SWT event has occurred EIFx External Interrupt Reque...

Page 395: ...interrupt IVOR0 core exception and the other is defined as the non maskable interrupt NMI IVOR1 core exception The NMI_SEL0 bit selects which exception will be generated by the SWT interrupt This bit...

Page 396: ...11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVF15 OVF14 OVF13 OVF12 OVF11 OVF10 OVF9 OVF8 OVF7 OVF6 OVF5...

Page 397: ...bit is cleared only by a reset 0 0 0 0 0 0 0 NMIRE0 1 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IREE15 IREE14 IREE13 IREE12 IREE11 IREE10...

Page 398: ...4 15 R NMIFE 1 1 This bit is cleared only by a reset 0 0 0 0 0 0 0 NMIFE0 1 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IFEE15 IFEE14 IFEE13...

Page 399: ...ter SIU_BASE 0x30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0...

Page 400: ...ailable in the packages listed in Chapter 1 Introduction Some of the I O functions controlled by the SIU PCRs are not available in the smaller packages The port enable logic for these PCRs is the same...

Page 401: ...ill be reflected in the corresponding GPDIx_x register Negating the IBE bit when the pin is configured as an output will reduce noise and power consumption DSC3 Drive strength control Controls the pad...

Page 402: ...k pullup down enable Controls whether the weak pullup down devices are enabled disabled for the pad Pullup down devices are enabled by default 0 Disable weak pull device for the pad 1 Enable weak pull...

Page 403: ...cified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching between input and output is hand...

Page 404: ...19 SIU_PCR0 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for inp...

Page 405: ...en configured as GPO set the OBE bit to one IBE 2 2 When configured as CS 2 or GPO set the IBE bit to one to reflect the pin state in the GPDI register When configured as GPI set the IBE bit to one DS...

Page 406: ...er an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data b...

Page 407: ...e OBE bit should be set to one IBE 2 2 When configured as ADDR 13 WE 2 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero redu...

Page 408: ...SIU_PCR10 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input...

Page 409: ...be set to one IBE 2 2 When configured as DATA 16 FR_A_TX or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power con...

Page 410: ...al Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 F...

Page 411: ...When configured as GPO the OBE bit should be set to one IBE 2 2 When configured as ADDR 19 FR_B_TX or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Sett...

Page 412: ...Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For...

Page 413: ...s no effect When configured as GPO the OBE bit should be set to one IBE 2 2 When configured as ADDR 22 DATA 22 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI r...

Page 414: ...SIU_PCR19 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input...

Page 415: ...igured as GPO the OBE bit should be set to one IBE 2 2 When configured as ADDR 25 DATA 25 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the I...

Page 416: ...SIU_PCR22 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input...

Page 417: ...ured as GPO the OBE bit should be set to one IBE 2 2 When configured as ADDR 28 DATA 28 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE...

Page 418: ...ues Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for ou...

Page 419: ...O the OBE bit should be set to one IBE 2 2 When configured as ADDR 31 ADDR 7 DATA 31 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bi...

Page 420: ...3 SIU_PCR28 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for inp...

Page 421: ...igured as GPO the OBE bit should be set to one IBE 2 2 When configured as DATA 2 ADDR 18 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IB...

Page 422: ...6 SIU_PCR31 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for inp...

Page 423: ...igured as GPO the OBE bit should be set to one IBE 2 2 When configured as DATA 5 ADDR 21 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IB...

Page 424: ...9 SIU_PCR34 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for inp...

Page 425: ...igured as GPO the OBE bit should be set to one IBE 2 2 When configured as DATA 8 ADDR 24 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IB...

Page 426: ...SIU_PCR37 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input...

Page 427: ...gured as GPO the OBE bit should be set to one IBE 2 2 When configured as DATA 11 ADDR 27 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IB...

Page 428: ...5 SIU_PCR40 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for inp...

Page 429: ...gured as GPO the OBE bit should be set to one IBE 2 2 When configured as DATA 14 ADDR 30 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IB...

Page 430: ...or Reserved Table 16 58 SIU_PCR43 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE...

Page 431: ...e OBE bit should be set to one IBE 2 2 When configured as BDIP or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces powe...

Page 432: ...d Table 16 61 SIU_PCR64 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set I...

Page 433: ...figured as GPO the OBE bit should be set to one IBE 2 2 When configured as OE or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to ze...

Page 434: ...ignal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output...

Page 435: ...e Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O...

Page 436: ...effect on MDO operation SRC WPE 4 4 The WPE bit should be set to zero for MDO operation WPS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 67 SIU_PCR76 PA values Signal Na...

Page 437: ...7 SIU GPIO I O 0b00 SIU_BASE 0xDC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE 1 1 This bit applies only to GPIO operation IBE 1 0 0 ODE 2 2 The ODE bit should be set to zero for MDO operati...

Page 438: ...cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction...

Page 439: ...applies only to GPIO operation IBE 1 0 0 ODE 2 2 The ODE bit should be set to zero for MDO operation HYS 3 3 The HYS bit has no effect on MDO operation SRC WPE 4 4 The WPE bit should be set to zero fo...

Page 440: ...ied using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching between input and output is handled...

Page 441: ...GPO the OBE bit should be set to one IBE 2 2 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power...

Page 442: ...O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change...

Page 443: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE 1 1 When configured as GPO the OBE bit should be set to one IBE 2 2 When configured as CAN_C_TX DSPI_D_PCS 3 or GPO the IBE bit may be set to one...

Page 444: ...R88 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OB...

Page 445: ...ured as SCI_A_RX the OBE bit has no effect When configured as GPO the OBE bit should be set to one IBE 2 2 When configured as EMIOS 15 or GPO the IBE bit may be set to one to reflect the pin state in...

Page 446: ...tion can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the...

Page 447: ...as GPO the OBE bit should be set to one IBE 3 3 When configured as DSPI_C_PCS 1 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to...

Page 448: ...A values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 f...

Page 449: ...function is not available on the MPC5644A Do not select 0b01 or 0b11 for the PA field OBE 2 2 When configured as GPO the OBE bit should be set to one IBE 3 3 When configured as DSPI_D_PCS 2 or GPO the...

Page 450: ...output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching betw...

Page 451: ...e PCSA 3 function is not available on the MPC5644A Do not select 0b01 or 0b11 for the PA field OBE 2 2 When configured as GPO the OBE bit should be set to one IBE 3 3 When configured as GPO the IBE bi...

Page 452: ...Reserved Table 16 91 SIU_PCR100 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE b...

Page 453: ...to one for master operation and set to zero for slave operation When configured as GPO the OBE bit should be set to one IBE 2 2 When configured as DSPI_B_SCK in slave operation the IBE bit should be...

Page 454: ...ame Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I...

Page 455: ...hen configured as DSPI_B_PCS 0 DSPI_D_PCS 2 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When...

Page 456: ...nimplemented or Reserved Table 16 97 SIU_PCR106 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using th...

Page 457: ...E bit should be set to one IBE 2 2 When configured as DSPI_B_PCS 3 or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces...

Page 458: ...ble 16 100 SIU_PCR109 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE...

Page 459: ...PI_C_PCS 0 DSPI Chip select I O 0b10 GPIO GPIO 110 SIU GPIO I O 0b00 SIU_BASE 0x122 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE 1 1 When configured as TCRCLKA or IRQ the OBE bit has no effe...

Page 460: ...PIO 114 are configured as outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC WPE WPS 3 3 The weak pull up down selection at reset for the...

Page 461: ...4 SIU_PCR115 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for in...

Page 462: ...or both ETPU_A 3 and GPIO 117 when configured as outputs IBE 2 2 The IBE bit must be set to one for both ETPU_A 3 and GPIO 117 when configured as inputs When configured as ETPU_A 15 or when ETPU_A 3 o...

Page 463: ...es Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for out...

Page 464: ...ne for both ETPU_A 6 and GPIO 120 when configured as outputs IBE 2 2 The IBE bit must be set to one for both ETPU_A 6 and GPIO 120 when configured as inputs When configured as ETPU_A 18 or when ETPU_A...

Page 465: ...iption I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions tha...

Page 466: ...or both ETPU_A 9 and GPIO 123 when configured as outputs IBE 2 2 The IBE bit must be set to one for both ETPU_A 9 and GPIO 123 when configured as inputs When configured as ETPU_A 21 or when ETPU_A 9 o...

Page 467: ...ignal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output...

Page 468: ...has no effect The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs IBE 2 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs When configure...

Page 469: ...unction can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as...

Page 470: ...to one for both ETPUA and GPIO when configured as inputs When configured as PCS or ETPUA or GPO outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 O...

Page 471: ...al Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 F...

Page 472: ...it must be set to one for both ETPUA and GPIO when configured as outputs IBE 2 2 The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs When configured as PCS or ETPUA or GPO...

Page 473: ...I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically suc...

Page 474: ...t be set to one for both ETPU_A 21 and GPIO 135 when configured as outputs IBE 2 2 When configured as FR_A_RX IRQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPD...

Page 475: ...Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For...

Page 476: ...puts IBE 2 2 When configured as DSPI_C_SCK_LVDS IRQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumpti...

Page 477: ...output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching betw...

Page 478: ..._A 27 and GPIO 141 when configured as outputs IBE 2 2 When configured as IRQ DSPI_C_SOUT_LVDS SOUTB or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Set...

Page 479: ...output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching betw...

Page 480: ...SIU_BASE 0x160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 PA OBE 1 1 When configured as ETPUA output or GPO the OBE bit should be set to one IBE 2 2 When configured as ETPUA output PCS or GPO the I...

Page 481: ...emented or Reserved Table 16 134 SIU_PCR145 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IB...

Page 482: ...8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE 1 1 The OBE bit must be set to one for both EMIOS 1 and GPIO 180 when configured as outputs IBE 2 2 When configured as ETPU the IBE bit may be set to one to refl...

Page 483: ...e an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamicall...

Page 484: ...IO 183 when configured as outputs IBE 2 2 When configured as ETPU the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power co...

Page 485: ...A values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 f...

Page 486: ...tputs IBE 2 2 When configured as ETPU the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must b...

Page 487: ...either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external d...

Page 488: ...the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for both EMIOS 10 and GPIO 189 when configured as inputs 0 0 ODE...

Page 489: ...lues Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for o...

Page 490: ...OBE 1 1 The OBE bit must be set to one for GPIO 192 when configured as an output IBE 2 2 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI regist...

Page 491: ...tion can be either an input or an output I O direction is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the...

Page 492: ...when configured as outputs IBE 2 2 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumpti...

Page 493: ...on is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching between input and outpu...

Page 494: ...0 0 0 0 0 0 0 0 1 WKP Unimplemented or Reserved Table 16 154 SIU_PCR198 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O directi...

Page 495: ...ne for both EMIOS 21 and GPIO 200 when configured as outputs IBE 2 2 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bi...

Page 496: ...on is specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching between input and outpu...

Page 497: ...to one 0 0 ODE HYS SRC WPE WPS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Unimplemented or Reserved Table 16 159 SIU_PCR203 PA values Signal Name Module Description I O1 2 1 In cases where an I O functi...

Page 498: ...be set to one to reflect the pin state in the corresponding GPDI register When configured as GPI the IBE bit should be set to one Setting the IBE bit to zero reduces power consumption 0 0 ODE HYS SRC...

Page 499: ...E bit should be set to one IBE 2 2 When configured as IRQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power con...

Page 500: ...ented or Reserved Table 16 164 SIU_PCR209 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an output I O direction is specified using the IBE...

Page 501: ...serted during reset OBE 2 2 When configured as IRQ the OBE bit has no effect When configured as GPO the OBE bit should be set to one IBE 3 3 When configured as IRQ or GPO the IBE bit may be set to one...

Page 502: ...Reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 Unimplemented or Reserved Table 16 167 SIU_PCR212 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be either an input or an ou...

Page 503: ...IBE and OBE bits are ignored PA value Primary WKPCFG Reset Config Connects eTPU and eMIOS pins to internal weak pull up or weak pull down devices after reset I 0b001 ALT1 NMI Reset Config Non Maskable...

Page 504: ...specified using the IBE and OBE bits Set IBE 1 for input or OBE 1 for output 2 For I O functions that change direction dynamically such as the external data bus switching between input and output is h...

Page 505: ...2 The WPE bit should be set to zero when configured as an analog input or MA 2 and set to one when configured as SDI WPS 3 3 The WPS bit should be set to one when configured as SDI W Reset 0 0 0 0 0...

Page 506: ...etween input and output is handled internally and the IBE and OBE bits are ignored PA value Primary AN 15 eQADC Analog input I 0b001 ALT1 FCK eQADC Free running clock O 0b010 ALT2 ETPU_A 29 eTPU eTPU...

Page 507: ...ld affects only the MCKO pin 10 ODE3 Open drain output enable Controls output driver configuration for the pads Either open drain or push pull driver configurations can be selected This feature applie...

Page 508: ...ices are used after reset or for pads in which the WKPCFG pin does not determine the reset weak pullup down state 0 Pulldown is enabled for the pad 1 Pullup is enabled for the pad Note This field affe...

Page 509: ...0 0 1 1 0 0 0 0 0 0 Unimplemented or Reserved Table 16 176 SIU_PCR221 PA values Signal Name Module Description I O PA value Primary MDO1 Nexus Nexus message data out O SIU_BASE 0x1FC 0 1 2 3 4 5 6 7...

Page 510: ...0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 179 SIU_PCR224 PA values Signal Name Module Description I O PA value Primary MSEO0 Nexus Nexus message start end out O SIU_BASE 0x202 0 1 2 3 4 5 6...

Page 511: ...egister SIU_PCR229 SIU_BASE 0x206 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE IBE 0 0 ODE HYS SRC WPE WPS W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Unimplemented or Reserved Table 16 182 SI...

Page 512: ...e direction dynamically such as the external data bus switching between input and output is handled internally and the IBE and OBE bits are ignored PA value Primary CLKOUT Clock Generation System cloc...

Page 513: ...igured as GPO the OBE bit should be set to one IBE 2 2 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero redu...

Page 514: ...ODE HYS SRC WPE WPS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Unimplemented or Reserved Table 16 189 SIU_PCR245 PA values Signal Name Module Description I O1 2 1 In cases where an I O function can be ei...

Page 515: ...d internally and the IBE and OBE bits are ignored PA value Primary CAL_CS2 Calibration bus Calibration chip select O 001 ALT1 CAL_ADDR 10 Calibration bus Calibration address bus I O 010 ALT2 CAL_WE 2...

Page 516: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA 0 0 DSC ODE HYS 0 0 WPE WPS W Reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 Unimplemented or Reserved Table 16 193 SIU_PCR340 PA values Signal Name Module Des...

Page 517: ...CAL_DATA 0 15 Calibration bus Calibration data bus I O SIU_BASE 0x2EC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 DSC ODE HYS 0 0 WPE WPS W Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Unimplemen...

Page 518: ...8 9 10 11 12 13 14 15 R 0 0 0 0 PA 0 0 DSC ODE HYS 0 0 WPE WPS W Reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 Unimplemented or Reserved Table 16 197 SIU_PCR345 PA values Signal Name Module Description I O P...

Page 519: ...DSI15 ETPU_A_30 EMIOS_12 GPIO365 SIU_PCR366 0x31C DSPI_B DSI16 ETPU_A_12 EMIOS_23 GPIO366 SIU_PCR367 0x31E DSPI_B DSI17 ETPU_A_13 EMIOS_15 GPIO367 SIU_PCR368 0x320 DSPI_B DSI18 ETPU_A_14 EMIOS_14 GPIO...

Page 520: ...SI0 ETPU_A_12 EMIOS_7 EMIOS_12 GPIO382 SIU_PCR 383 0x33E DSPI_C DSI1 ETPU_A_13 EMIOS_16 EMIOS_13 GPIO383 SIU_PCR 384 0x340 DSPI_C DSI2 ETPU_A_14 EMIOS_17 EMIOS_14 GPIO384 SIU_PCR 385 0x342 DSPI_C DSI3...

Page 521: ...SPI_C DSI13 ETPU_A_9 EMIOS_9 GPIO395 SIU_PCR 396 0x358 DSPI_C DSI14 ETPU_A_10 EMIOS_10 GPIO396 SIU_PCR 397 0x35A DSPI_C DSI15 ETPU_A_11 EMIOS_11 GPIO397 SIU_PCR 398 0x35C DSPI_C DSI16 ETPU_A_23 EMIOS_...

Page 522: ...guration Register the SIU_GPDIx_x register reflects the actual state of the output pin The definition of the SIU_GPDIx_x registers is given in Figure 16 200 and Figure 16 201 Each of the GPDI bits cor...

Page 523: ...eld selects the trigger source for eQADC CFIFO4 and so on Additionally each SIU_ETISR field offers selection among a group of signals using the corresponding field in the SIU_ISEL3 register SIU_BASE 0...

Page 524: ...e SIU_ISEL3 register Figure 16 203 eQADC Trigger Input Select Register SIU_ETISR SIU_BASE 0x900 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TSEL5 TSEL4 TSEL3 TSEL2 TSEL1 TSEL0 0 0 0 0 W Reset 0 0 0 0 0 0...

Page 525: ...pin 4 5 TSEL3 eQADC Trigger Input Select 3 The eQADC trigger 3 input is as follows 00 eTSEL3 described in SIU_ISEL3 01 eTPU_A 28 channel 10 eMIOS 14 channel 11 ETRIG 1 pin 6 7 TSEL2 eQADC Trigger Inp...

Page 526: ...input is specified by ESEL15 as follows 00 IRQ 15 pin 01 DSPI_B 15 deserialized output 10 DSPI_C 0 deserialized output 11 DSPI_D 1 deserialized output 2 3 ESEL14 External IRQ Input Select 14 IRQ 14 in...

Page 527: ...RQ Input Select 6 IRQ 6 is multiplexed on the TCRCLK_B pin which is not available in any of the MPC5644A packages IRQ 6 input is specified by ESEL6 as follows 00 IRQ 6 pin 01 DSPI_B 6 deserialized out...

Page 528: ...eMIOS 14 1 The DISR is sometimes referred to as ISEL2 SIU_BASE 0x908 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 SINSELB SSSELB SCKSELB TRIGSELB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16...

Page 529: ...SPI_C is specified by SSSELC as follows 00 DSPI_C_PCS 0 pin 01 Reserved 10 DSPI_B_PCS 0 Master 11 DSPI_D_PCS 0 Master 20 21 SCKSELC DSPI_C Clock Input Select The source of the clock input of DSPI_C wh...

Page 530: ...input of DSPI_D when in slave mode is specified by SCKSELD as follows 00 DSPI_D_SCK pin 01 Reserved 10 DSPI_B_SCK Master 11 DSPI_C_SCK Master 30 31 TRIGSELD DSPI_D Trigger Input Select The source of...

Page 531: ...0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 eMIOS10 AND PIT2 1 0 1 0 1 eMIOS10 AND PIT3 1 0 1 1 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 0 1 Reserved 1 1 0 1 0 Reserve...

Page 532: ...Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1 1 eTPU31 1 0 0 0 0 Reserved 1 0 0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 eMIOS11 AND PIT2 1 0 1 0 1 eMIOS11 A...

Page 533: ...gger 0 0 1 1 0 Reserved 0 0 1 1 1 BOOTCFG 1 eTRIG3 0 1 0 0 0 eTPU30 AND PIT0 0 1 0 0 1 eTPU30 AND PIT1 0 1 0 1 0 Reserved 0 1 0 1 1 Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1...

Page 534: ...igger 0 0 1 1 0 Reserved 0 0 1 1 1 PLLREF eTRIG2 0 1 0 0 0 eTPU30 AND PIT0 0 1 0 0 1 eTPU30 AND PIT1 0 1 0 1 0 Reserved 0 1 0 1 1 Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1 1...

Page 535: ...gger 0 0 1 1 0 Reserved 0 0 1 1 1 BOOTCFG 1 eTRIG3 0 1 0 0 0 eTPU30 AND PIT0 0 1 0 0 1 eTPU30 AND PIT1 0 1 0 1 0 Reserved 0 1 0 1 1 Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1...

Page 536: ...igger 0 0 1 1 0 Reserved 0 0 1 1 1 PLLREF eTRIG2 0 1 0 0 0 eTPU30 AND PIT0 0 1 0 0 1 eTPU30 AND PIT1 0 1 0 1 0 Reserved 0 1 0 1 1 Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1 1...

Page 537: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 ESEL3 0 0 0 ESEL2 0 0 0 ESEL1 0 0 0 ESEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16...

Page 538: ...I_B 13 deserialized output 1 eTPU channel 24 SIU_BASE 0x924 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 2...

Page 539: ...tegrator reset signal 0 1 0 1 1 Reserved 0 1 1 0 0 eTPU28 0 1 1 0 1 eTPU29 0 1 1 1 0 eTPU30 0 1 1 1 1 eTPU31 1 0 0 0 0 Reserved 1 0 0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 eMIOS...

Page 540: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HSELB ZSELB HSELA ZSELA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 214 Decimation filter...

Page 541: ...m reset negates the value in this bit depends on the censorship control word and the boot configuration bits 0 Nexus disable input signal is negated 1 Nexus disable input signal is asserted 16 29 Rese...

Page 542: ...lock Division Factor The ENGDIV field specifies the frequency ratio between the system clock and the ENGCLK The ENGCLK frequency is divided from the system clock frequency according to the following e...

Page 543: ...s Division Factor The EBDF field specifies the frequency ratio between the system clock and CLKOUT The EBDF field must not be changed during an external bus access or while an access is pending 00 Ext...

Page 544: ...gister SIU_CBRL The SIU_CBRL register holds the 32 bit value that is compared against the value in the SIU_CARL register The CMPBL field is read write and is reset by the IP Green Line synchronous res...

Page 545: ...0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x9A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_SRC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 2...

Page 546: ...e for the system clock ipg_clk Note that the SYSCLKDIV divider is required in addition to the RFD to allow the other sources for the system clock 16 MHz IRC and OSC to be divided down to slowest frequ...

Page 547: ...TP EBI stop request When asserted a stop request is sent to the external bus controller which handles the calibration interface 1 Stop mode request 0 Normal operation 8 ADCSTP eQADC stop request When...

Page 548: ...is sent to the FlexCAN A module 1 Stop mode request 0 Normal operation 20 SPIDSTP DSPI D stop request When asserted a stop request is sent to the DSPI C 1 Stop mode request 0 Normal operation 21 SPIC...

Page 549: ...a stop acknowledge was received from the following modules CPU cross bar peripheral bridge system RAM Flash STM DMA 1 Stop mode request 0 Normal operation 1 3 Reserved 4 NSETIACK eTPU Nexus module NS...

Page 550: ...edge When asserted indicates that a stop acknowledge was received from the periodic interrupt timer module 1 Stop mode request 0 Normal operation 14 16 Reserved 17 CNCACK FlexCAN C stop acknowledge Wh...

Page 551: ...n mechanism that enables the mapping to change when a specified instruction address is reached or a specified load store address is accessed Synchronization is implemented using Watchpoint Event 2 out...

Page 552: ...ontents of this register are not used to select the alternate MMU mapping 1 The contents of this register are used to select the alternate MMU mapping defined by EXT_PID6 and EXT_PID7 EXT_PID_SYNC0 1...

Page 553: ...aracteristics of external pins The multiplexed function of a pin selection of pull up or pull down devices the slew rate of I O signals open drain mode for output pins hysteresis on input pins and the...

Page 554: ...owing sections for more information Section 16 6 6 External Interrupt Status Register SIU_EISR Section 16 6 11 IRQ Rising Edge Event Enable Register SIU_IREER Section 16 6 12 External IRQ Falling Edge...

Page 555: ...functionality for this device Each device pin that has GPIO functionality has an associated Pin Configuration Register in the SIU where the GPIO function is selected for the pin In addition each devi...

Page 556: ...21 eQADC trigger input multiplexing example The remaining ADC trigger inputs are multiplexed in the same manner Note that if an ETRIG input is connected to an eTPU or eMIOS channel the external pin us...

Page 557: ...tiple transfer operation To support multiple DSPIs transfer operations an input multiplexor is required for the SIN SS SCK IN and trigger signals of each DSPI These DSPI input sources can be a pin or...

Page 558: ...System Integration Unit SIU MPC5644A Microcontroller Reference Manual Rev 6 558 Freescale Semiconductor...

Page 559: ...to control system clock source and programming of PLL parameter Clock gating for individual modules controlled by either SIU_HLT or module s MDIS register bit Refer to Table 5 2 MDIS support Chapter 5...

Page 560: ...ency synthesis resolution Reduced frequency divider for reducing the FMPLL output clock frequency without forcing the FMPLL to relock Input clock frequency range from 4 MHz to 20 or 40 MHz1 before the...

Page 561: ...d to a package pin called PLLREF After reset a different operational mode can be selected by writing to FMPLL_ESYNCR1 CLKCFG The available modes are specified in Table 17 2 At reset the FMPLL is enabl...

Page 562: ...same and frequency modulation is not available Bypass mode with external reference is the default mode at reset if the PLLREF input is driven low After reset this mode can be entered by programming FM...

Page 563: ...ns Signal I O Description PLLREF I O PLL reference Determines the reset state of the CLKCFG 2 bit in FMPLL_ESYNCR1 The PLLREF pin must be kept stable during system reset After reset this pin has no ef...

Page 564: ...his model it is possible to change the FMPLL operating mode back and forth between bypass and normal modes by programming FMPLL_ESYNCR1 CLKCFG The reset value of FMPLL_ESYNCR1 EMODE is determined by t...

Page 565: ...be cleared 1 3 PREDIV Predivider This 3 bit field controls the value of the divider on the input clock The output of the predivider circuit generates the reference clock to the FMPLL analog loop The v...

Page 566: ...dition when LOCEN 1 LOCRE has no effect when LOCEN 0 If the LOCF bit in the SYNSR indicates a loss of clock condition setting the LOCRE bit causes immediate reset In bypass mode with crystal reference...

Page 567: ...gacy mode which modifies the PREDIV or MFD fields or write to FMPLL_ESYNCR1 in enhanced mode which modifies the EMODE EPREDIV EMFD or CLKCFG 1 0 fields Furthermore it is not asserted if the loss of lo...

Page 568: ...e of the CLKCFG 2 bit of the FMPLL_ESYNCR1 0 External clock reference 1 Crystal oscillator reference 27 LOCKS Sticky FMPLL lock status bit This bit is set by the lock detect circuitry when the FMPLLL...

Page 569: ...g 1 or asserting reset The LOCF flag is not asserted while the FMPLL is in bypass mode See Section 17 5 4 Loss of clock detection for information on which operating modes and conditions can this flag...

Page 570: ...FMPLL controlled by ESYNCR1 ESYNCR2 1 3 CLKCFG Clock configuration This 3 bit field is used to change the operating mode of the FMPLL Bit 2 is not writable to 0 while bit 1 is 1 The reset state of bit...

Page 571: ...e by 96 110_0001 Invalid 111_1111 Invalid Offset 0x000C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 LOCEN LOLRE LOCRE LOLIRQ LOCIRQ 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 572: ...if the reference clock fails even if LOCRE 0 or even if LOCEN 0 The LOCRE bit has no effect in bypass mode with external reference In this mode the reference clock is not monitored at all See Section...

Page 573: ...ting another write access to this register Any write attempt while the BSY flag is set will have no effect 0 Write to the FMPLL_SYNFMMR is allowed 1 The FMPLL is still busy processing the previous cha...

Page 574: ...nt step This 14 bit field is the binary equivalent of the incstep variable derived from the formula where MD represents the peak modulation depth in percentage MD for centered modulation 2 MD for modu...

Page 575: ...he EMODE EPREDIV EMFD of CLKCFG 1 2 fields of the FMPLL_ESYNCR1 are changed1 Upon any of these events an internal timer is initialized to count 64 cycles of the PLL input clock During this period the...

Page 576: ...reated from good clock sources Whether the clocks are monitored or not is determined by the clock operating mode and control bits in the FMPLL registers as shown in Table 17 12 In bypass mode with cry...

Page 577: ...FMPLL failure the system clock is connected back to the FMPLL output If the reference fails in normal mode then no backup clock selection occurs and the FMPLL output continues to be the system clock...

Page 578: ...regardless the state of the reference clock Exit from reset is not affected by the state of the FMPLL output because the FMPLL clock is not monitored in bypass mode 17 5 4 3 Loss of clock interrupt r...

Page 579: ...igure 17 8 Triangular frequency modulation Table 17 14 Loss of clock interrupt request Operating mode LOCEN1 1 LOCEN is the loss of clock enable bit in either FMPLL_SYNCR or FMPLL_ESYNCR2 depending on...

Page 580: ...ut frequency 4 MHz Load divider EMFD 64 Input divider 1 VCO frequency 4 MHz 64 256 MHz PLL output frequency 256 MHz ERFD Center spread MODSEL 0 Modulation frequency 24 kHz Modulation depth 2 0 4 peak...

Page 581: ...parameters it takes some time until these parameters get propagated to the PLL analog circuitry During this time the BSY bit gets asserted The modulation must only be enabled when the FM parameters ha...

Page 582: ...Frequency modulated phase locked loop FMPLL MPC5644A Microcontroller Reference Manual Rev 6 582 Freescale Semiconductor...

Page 583: ...t Status Register ECSM_MRSR Registers for capturing information on memory errors if error correcting codes ECC are implemented 18 3 Module memory map The Error Correction Status Module does not includ...

Page 584: ...e of reset that occurred Only one bit is set at any time in the ECSM_MRSR reflecting the cause of the most recent reset as signalled by device reset input signals The ECSM_MRSR can only be read from t...

Page 585: ...s the ECSM output signal enter_low_power_mode to be set This in turn causes the selected external low power mode to be entered and the appropriate clock signals disabled In most implementations there...

Page 586: ...VL 0 3 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 18 2 Miscellaneous Wakeup Control Register ECSM_MWCR Table 18 3 ECSM_MWCR field description Name Description 0 ENBWCR Enable WCR 0 MWCR is disabled...

Page 587: ...M_FEMR Flash ECC Attributes Register ECSM_FEAT Flash ECC Data Register ECSM_FEDR RAM ECC Address Register ECSM_REAR RAM ECC Syndrome Register ECSM_PRESR RAM ECC Master Number Register ECSM_REMR RAM EC...

Page 588: ...ng which types of memory errors are reported In all systems with ECC the occurrence of a non correctable error causes the current access to be terminated with an error condition In many cases this err...

Page 589: ...o captured in the ECSM_REAR ECSM_PRESR ECSM_REMR ECSM_REAT and ECSM_REDR registers 3 EF1BR Enable Flash 1 bit Reporting 0 Reporting of single bit platform flash corrections is disabled 1 Reporting of...

Page 590: ...able error ECSM_ECC_IRQ ECSM_ECC1BIT_IRQ 1 bit correction ECSM_ECC2BIT_IRQ noncorrectable error where the combination of a properly enabled category in the ECSM_ECR and the detection of the correspond...

Page 591: ...platform flash correction has been detected This bit can only be set if ECSM_ECR EF1BR is asserted The occurrence of a properly enabled single bit flash correction generates an ECSM ECC interrupt req...

Page 592: ...e noted that while the ECSM_EEGR is associated with the RAM similar capabilities exist for the flash that is the ability to program the non volatile memory with single or double bit errors is supporte...

Page 593: ...event in the RAM After this bit has been enabled to generate another continuous 1 bit data inversion it must be cleared before being set again to correctly re enable the error generation logic 3 FR11...

Page 594: ...efined by the bit position specified in ERRBIT 6 0 and the overall odd parity bit on the first write operation after this bit is set The normal ECC generation takes place in the RAM controller but the...

Page 595: ...bit memory banks even bank and odd bank The following association between the ERRBIT field and the corrupted memory bit is defined if ERRBIT 0 then RAM 0 of the odd bank is inverted if ERRBIT 1 then...

Page 596: ...a 4 bit register for capturing the XBAR bus master number of the last properly enabled ECC event in the flash memory Depending on the state of the ECC Configuration Register an ECC event in the flash...

Page 597: ...and the appropriate flag FNCE in the ECC Status Register to be asserted This register can only be read from the IPS programming model any attempted write is ignored Register address ECSM Base 0x0056 0...

Page 598: ...EDR registers and the appropriate flag FNCE in the ECC Status Register to be asserted The data captured on a multi bit non correctable ECC error is undefined This register can only be read from the IP...

Page 599: ...s register can only be read from the IPS programming model any attempted write is ignored Register address ECSM Base 0x58 0x5C 0xFFF4_0058 0xFFF4_005C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEDH 31 1...

Page 600: ...priate flag RNCE in the ECC Status Register to be asserted The ECSM_PRESR can only be read from the IPS programming model any attempted write is ignored Register address ECSM Base 0x0060 0xFFF4_0060 0...

Page 601: ...zed syndrome encoding for the entire 39 bit 32 bit data 7 bit ECC code word of each bank for single bit errors Syndrome values for non correctable errors are not defined For correctable single bit err...

Page 602: ...29 0x70 DATA ODD BANK 14 0x73 DATA ODD BANK 15 0x75 DATA ODD BANK 16 0x76 DATA ODD BANK 17 0x79 DATA ODD BANK 18 0x7A DATA ODD BANK 19 0x7C DATA ODD BANK 20 0x7F DATA ODD BANK 30 0x81 ECC EVEN 0 0x82...

Page 603: ...to be asserted This register can only be read from the IPS programming model any attempted write is ignored 0xCF DATA EVEN BANK 21 0xD1 DATA EVEN BANK 6 0xD2 DATA EVEN BANK 7 0xD4 DATA EVEN BANK 8 0x...

Page 604: ...ECSM_REAT and ECSM_REDR registers and the appropriate flag RNCE in the ECC Status Register to be asserted The ECSM_REAT register is read only Register address ECSM Base 0x0066 0xFFF4_0066 0 1 2 3 4 5...

Page 605: ...a multi bit non correctable ECC error is undefined Since the RAM controller calculates ECC on a 32 bit boundary only the 32 bit piece of data containing the error is recorded in the lower 32 bit word...

Page 606: ...Reset 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 R REDL 31 16 W Reset 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R REDL 15 0 W Reset Unimplemented Figure 18 15 RAM ECC Data Register ECSM_RED...

Page 607: ...four 32 bit compare channels with a separate interrupt source for each channel The counter is driven by the system clock divided by an 8 bit prescale value 1 to 256 19 2 2 Modes of operation The STM...

Page 608: ...page 19 610 0x0018 STM Channel 0 Compare Register STM_CMP0 32 R W on page 19 611 0x001C Reserved 0x0020 STM Channel 1 Control Register STM_CCR1 32 R W on page 19 610 0x0024 STM Channel 1 Interrupt Reg...

Page 609: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 1 STM Control Register STM_CR Table 19 2 STM_CR field description Field Description CPS Counter Prescaler Selects the clock divide value for the prescaler 1 256 0x0...

Page 610: ...ield Description CNT Timer count value used as the time base for all channels When enabled the counter increments at the rate of the system clock divided by the prescale value Offset 0x10 0x10 n Acces...

Page 611: ...Table 19 5 STM_CIRn field description Field Description CIF Channel Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit Writing a 0 has no effect 0 No interrupt request 1 Int...

Page 612: ...STM_CR TEN bit When enabled in normal mode the counter continuously increments When enabled in debug mode the counter operation is controlled by the STM_CR FRZ bit When the STM_CR FRZ bit is set the...

Page 613: ...ammable selection of reset or interrupt on an initial time out Programmable selection of fixed or keyed servicing Master access protection Hard and soft configuration lock bits 20 1 3 Modes of operati...

Page 614: ...WT_MCR contains fields for configuring and controlling the SWT The reset value of this register is device specific Some devices can be configured to automatically clear the SWT_MCR WEN bit during the...

Page 615: ...e two pseudorandom key values are used to service the watchdog RIA Reset on Invalid Access 0 Invalid access to the SWT generates a bus error 1 Invalid access to the SWT causes a system reset if WEN 1...

Page 616: ...l Allows the watchdog timer to be stopped when the device enters debug mode 0 SWT counter continues to run in debug mode 1 SWT counter is stopped in debug mode WEN Watchdog Enabled 0 SWT is disabled 1...

Page 617: ...10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WTO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 Table 20 4 SWT_TO Register field description Field Descr...

Page 618: ...e This field is used to service the watchdog and to clear the soft lock bit SWT_MCR SLK If the SWT_MCR KEY bit is set two pseudorandom key values are written to service the watchdog see Section 20 4 F...

Page 619: ...either case when locked the SWT_MCR SWT_TO SWT_WN and SWT_SK registers are read only The hard lock is enabled by setting the SWT_MCR HLK bit which can only be cleared by a reset The soft lock is enab...

Page 620: ...erate a bus error or reset depending on the value of the SWT_MCR RIA bit For example if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service sequence must be performe...

Page 621: ...nslation for all internal device resources MMU configuration to boot user application compiled as Power Architecture technology code or as Freescale VLE code Passes control to user application code in...

Page 622: ...0 to 0xFFFF_FFFF The actual code size of the BAM program is less than 4 KB and starts at 0xFFFF_F000 repeating itself down every 4 kilobytes in the BAM address space The CPU starts the BAM program exe...

Page 623: ...ion of RSTOUT before user code starts First the BAM program configures the core MMU to allow access to all device internal resources according to Table 21 2 This MMU setup remains the same for interna...

Page 624: ...al Flash memory Table 21 2 MMU configuration for internal flash boot TLB entry Region Logical base address Physical base address Size Attributes 0 Peripheral Bridge B1 and BAM 1 This device has only a...

Page 625: ...blic password fixed value of the 0xFEED_FACE_CAFE_BEEF or needs to be compared to a Flash password 64 bit data stored in the shadow row of internal flash at address 0x00FF_FDD8 If the bit is set the B...

Page 626: ...ntrol to Table 21 6 provides possible RCHW locations in the internal flash When booting from the external flash device the RCHW should reside in the very first 16 bit half word of the flash Figure 21...

Page 627: ...5 217 system clocks PS0 Port size Defines the width of the data bus connected to the memory on CS0 After system reset CS0 is changed to a 16 bit port by the BAM which fetches the RCHW from either 16...

Page 628: ...ns If a valid RCHW is not found the BAM program proceeds to check of possibility of booting to the serial boot mode 21 5 4 1 Finding reset configuration half word The BAM searches the internal Flash m...

Page 629: ...G Nexus is disabled and only JTAG BSDL commands can be used Access to the Nexus JTAG clients on a censored device requires inputting the proper password into the JTAG Censorship Control Register durin...

Page 630: ...erased without reprogramming a new valid password before a reset it will contain an illegal password and the debug port will be inaccessible 4 Subsequent resets will clear the JTAG censor password reg...

Page 631: ...Pad configuration Function Pad configuration CN_A_TX GPIO CN_A_TX Push Pull output with medium slew rate CN_A_TX Push Pull output with medium slew rate GPIO CN_A_RX GPIO CN_A_RX Input with pull up and...

Page 632: ...g is configured as shown in Figure 21 7 Figure 21 7 CAN bit timing The BAM program ignores CAN errors and all received data is assumed to be good and is echoed out on the CN_A_TX signal It is the resp...

Page 633: ...s back received data with message ID of 0x3 When the SCI is used for serial download the data has to be sent on a byte by byte basis the device transmits back the received data 21 5 5 4 Download proto...

Page 634: ...ppen if the device RAM is protected by 64 bit ECC code Once the buffered data is written to the RAM the BAM program refreshes the SWT watchdog NOTE Only system RAM supports 64 bit writes therefore att...

Page 635: ...etection The host has to send a zero byte to allow the device to detect the serial link baud rate The host transmits 1 start bit 8 zero data bits and 1 stop bit The device does not echo it The device...

Page 636: ...PSEG2 8 1 3 3 2 9 2 3 3 2 10 3 3 3 2 11 4 3 3 2 12 3 4 4 2 13 4 4 4 3 14 5 4 4 3 15 6 4 4 4 16 7 4 4 3 17 8 4 4 3 18 7 5 5 4 19 8 5 5 4 20 7 6 6 4 21 8 6 6 4 22 7 6 6 4 23 8 6 6 4 24 7 7 7 4 25 8 7 7...

Page 637: ...e user code If no valid RCHW was read BAM switches to the serial boot mode 21 5 6 1 EBI Configuration for External Bus Interface Boot Mode The BAM program sets up EBI related registers as shown in Tab...

Page 638: ...Selects WE 0 BE 0 function sets pad to 20 pF drive strength enables weak pull device for pad and enables pullup SIU_PCR 68 69 0x443 Selects OE and TS functions sets pads to 20 pF drive strength enable...

Page 639: ...s The MPC5644A has one eMIOS200 module that implements twenty four 24 bit counters The overall architecture of the eMIOS200 resembles that of its predecessor the MIOS The MIOS timer block provided a f...

Page 640: ...mported and used by the channels Global enable feature for all eMIOS and eTPU timebases Dedicated pin for each channel not available on all package types Each channel 0 23 supports the following funct...

Page 641: ...channel When entering this mode the unified channel registers contents are frozen but remain available for read and write access through the IP interface 22 2 3 Channel configurations Table 22 1 show...

Page 642: ...ncy Modulation Buffered OPWFMB on page 22 674 Output Pulse Width Modulation Buffered OPWMB on page 22 679 Table 22 2 MPC5644A eMIOS memory map Offset from EMIOS_BASE 0xC3FA_0000 Register Location Glob...

Page 643: ...2 Control Register on page 22 655 0x0070 EMIOS_CSR 2 Status Register on page 22 659 0x0074 EMIOS_ALTA 2 1 Alternate A Register on page 22 660 0x0078 0x007F Reserved Channel 3 registers 0x0080 EMIOS_C...

Page 644: ...NTR 6 Counter Register on page 22 654 0x00EC EMIOS_CCR 6 Control Register on page 22 655 0x00F0 EMIOS_CSR 6 Status Register on page 22 659 0x00F4 EMIOS_ALTA 6 1 Alternate A Register on page 22 660 0x0...

Page 645: ...10 B Register on page 22 653 0x0168 EMIOS_CCNTR 10 Counter Register on page 22 654 0x016C EMIOS_CCR 10 Control Register on page 22 655 0x0170 EMIOS_CSR 10 Status Register on page 22 659 0x0174 EMIOS_...

Page 646: ...EMIOS_CADR 14 A Register on page 22 653 0x01E4 EMIOS_CBDR 14 B Register on page 22 653 0x01E8 EMIOS_CCNTR 14 Counter Register on page 22 654 0x01EC EMIOS_CCR 14 Control Register on page 22 655 0x01F0...

Page 647: ...0x0258 0x025F Reserved Channel 18 registers 0x0260 EMIOS_CADR 18 A Register on page 22 653 0x0264 EMIOS_CBDR 18 B Register on page 22 653 0x0268 EMIOS_CCNTR 18 Counter Register on page 22 654 0x026C E...

Page 648: ...02D4 EMIOS_ALTA 21 1 Alternate A Register on page 22 660 0x02D8 0x02DF Reserved Channel 22 registers 0x02E0 EMIOS_CADR 22 A Register on page 22 653 0x02E4 EMIOS_CBDR 22 B Register on page 22 653 0x02E...

Page 649: ...0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R GPRE 0 7 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 2 eMIOS200 Module Configuration Register EMIOS_MCR Table 22 3 EMIO...

Page 650: ...s A Note If ETB is set to select STAC as the counter bus A source the GTBE must be set to enable the STAC to counter bus A See the STAC bus configuration register ETPU_REDCR section of the eTPU chapte...

Page 651: ...eMIOS200 Global Flag Register EMIOS_GFR Table 22 4 EMIOS_GFR field description Field Description Fn FLAG The EMIOS_GFR is a read only register that groups the FLAG bits from all channels These bits a...

Page 652: ...epending on the operation mode transfer may occur immediately or in the next period Unless stated otherwise transfer occurs immediately 1 Transfers disabled Address EMIOS_BASE 0xC3FA_0000 0x000C Acces...

Page 653: ...nding on the channel s configuration it may or may not have the EMIOS_CBDR This means that if at least one mode that requires the register is implemented then the register is present Otherwise it is a...

Page 654: ...y have an internal counter or not If at least one mode that requires the counter is implemented the counter is present otherwise it is not SAIC1 A2 B2 B2 SAOC1 A2 A1 B2 B2 IPWM A2 B1 IPM A2 B1 DAOC A2...

Page 655: ...CR field description Field Description FREN Freeze Enable The FREN bit if set and validated by bit EMIOS_MCR FRZ freezes all registers values when in debug mode allowing the MCU to perform debug funct...

Page 656: ...is used as an interrupt or as a DMA request 0 FLAG overrun assigned to interrupt request 1 FLAG overrun assigned to DMA request IF Input Filter The IF bits control the programmable input filter select...

Page 657: ...Match B For output modes the FORCMB bit is equivalent to a successful comparison on comparator B except that the FLAG bit is not set This bit is cleared by reset and is always read as 0 This bit is va...

Page 658: ...this bit has no effect 0 Trigger on a falling edge 1 Trigger on a rising edge For output modes the EDPOL bit is used to select the logic level on the output pin 0 A match on comparator A clears the ou...

Page 659: ...0 0 0 0 0 0 0 0 0 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVFL 0 0 0 0 0 0 0 0 0 0 0 0 UCIN UCOUT FLAG W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 660: ...re 22 12 shows the eMIOS200 Unified Channel1 block diagram Each Unified Channel consists of Counter bus selector which selects the time base to be used by the channel for all timing functions UCOUT Un...

Page 661: ...input events Programmable input filter which ensures that only valid pin transitions are received by channel Programmable input edge detector which detects the rising falling or either edges An output...

Page 662: ...ization a set of registers is shared by the modes thus providing sequential events to be stored The Datapath block provides the channel A and B registers the internal time base and comparators Multipl...

Page 663: ...n input MODE 6 0 and output MODE 6 1 modes NOTE It is required that when changing MODE 0 6 the application software goes to GPIO mode first in order to reset the channel s internal functions properly...

Page 664: ...is transferred to it Along with the match the FLAG bit is set to indicate that the output compare match has occurred Writing to EMIOS_CADR n stores the value in register A2 and reading to register EM...

Page 665: ...ites to EMIOS_CADR n The FLAG is set at the same time a match occurs see Figure 22 18 NOTE The channel internal counter in SAOC mode is free running It starts counting as soon as the SAOC mode is ente...

Page 666: ...d time base is latched into register A2 and at the same time the FLAG bit is set and the content of register B2 is transferred to register B1 and to register A1 If subsequent input capture events occu...

Page 667: ...lways provides coherent data If no coherent data is required for any reason the sequence of reads should be inverted therefore EMIOS_CBDR n should be read prior to EMIOS_CADR n Note that even in this...

Page 668: ...n return the values in register A2 and B1 respectively In order to allow coherent data reading EMIOS_CADR n forces A1 content be transferred to B1 register and disables transfers between B2 and B1 The...

Page 669: ...1 register occurs and is disabled on the next B match Comparators A and B are enabled and disabled independently The output flip flop is set to the value of EDPOL when a match occurs on comparator A a...

Page 670: ...re 22 24 Double Action Output Compare with FLAG set on both matches selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 A1 value1 B1 value2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0...

Page 671: ...rder to avoid the counter wrap condition make sure its value is within the 0x1 to A1 register value range when the MCB mode is entered MODE 6 bit selects internal clock source if cleared or external i...

Page 672: ...s loaded with the A2 register value at the cycle boundary Thus any value written to the A2 register within cycle n will be updated to A1 at the next cycle boundary and therefore will be used on cycle...

Page 673: ...llowing to delay the A1 register update for synchronization purposes Figure 22 28 MCB Mode A1 Register Update in Up Counter Mode Figure 22 29 describes the A1 register update in up down counter mode N...

Page 674: ...nel internal counter to wrap at the maximum counter value which is 0xFF_FFFF for a 24 bit counter After the counter wrap occurs it returns to 0x1 and resume normal OPWFMB mode operation Thus in order...

Page 675: ...s used to trigger the output pin transition instead of the negedge used when A1 0x1 Note that A1 posedge match signal from cycle n 1 occurs at the same time as B1 negedge match signal from cycle n Thi...

Page 676: ...to delay the A1 and B1 registers update for synchronization purposes In Figure 22 32 it is assumed that both the channel and global prescalers are set to 0x1 each divide ratio is two meaning that the...

Page 677: ...ive high signals and a high to low transition at A1 match In this case EDPOL should be set to 0 Note that both the channel and global prescalers are set to 0x0 each divide ratio is one meaning that th...

Page 678: ...flip flop to the level corresponding to a match on comparators A or B respectively Similarly to a B1 match FORCMB sets the internal counter to 0x1 The FLAG bit is not set by the FORCMA or FORCMB bits...

Page 679: ...more information about A1 and B1 registers update FLAG can be generated at B1 matches when MODE 5 is cleared or in both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparators...

Page 680: ...used instead of the negedge to transition the output flip flop Figure 22 36 describes the channel operation for 0 duty cycle Note that the A1 match posedge signal occurs at the same time as the B1 0x...

Page 681: ...ion at the following A1 or B1 match Note that the Output Disable does not modify the Flag bit behavior Note that there is one system clock delay between the assertion of the output disable signal and...

Page 682: ...duty cycle signal is generated 22 5 1 2 Input programmable filter IPF The IPF ensures that only valid input pin transitions are received by the channel edge detector A block diagram of the IPF is show...

Page 683: ...s regarded as a glitch and it is not passed on to the edge detector A timing diagram of the input filter is shown in Figure 22 40 Figure 22 40 Input programmable filter example The filter is not disab...

Page 684: ...P bus interface unit BIU The BIU provides the interface between the Internal Interface Bus IIB and the Peripheral Bus allowing communication among all submodules and this IP interface The BIU allows 8...

Page 685: ...ct of freeze on the STAC client submodule When bit EMIOS_MCR FRZ is set and the module is in debug mode the operation of the STAC client submodule is not affected that is there is no freeze function i...

Page 686: ...n Application information On resetting the eMIOS200 the channels enter GPIO input mode 22 6 1 Considerations Before changing an operating mode the UC must be programmed to GPIO mode and EMIOS_CADR n a...

Page 687: ...ally in GPIO mode 1 global Disable global prescaler 2 timebase channel Disable channel prescaler 3 timebase channel Write initial value at internal counter 4 timebase channel Set A B register 5 timeba...

Page 688: ...Configurable Enhanced Modular IO Subsystem eMIOS200 MPC5644A Microcontroller Reference Manual Rev 6 688 Freescale Semiconductor...

Page 689: ...nnels with channel routing capability Innovative concept of Shared Modulation Control Innovative concept of dynamic timer allocation 3 outputs per channel to support different driver architectures Fle...

Page 690: ...ered only when all channels are disabled by REACM_CHCRn CHEN 00 23 1 2 3 Channel modes After a channel is in enabled mode that channel is also said to be in the normal mode of operation which means it...

Page 691: ...sor Input Register REACM_SINR allows direct access for write to the TAG and ADC result values input to the reaction module This software control may be used for module debug purposes Please see Figure...

Page 692: ...ation Word address based on the data programmed in the internal configuration register 3 A Modulation word is selected by the reaction channel 4 The selected Modulation Word generates the address for...

Page 693: ...ess only initiates after the channel is moved to the active state The following sections describe this process in more detail After the activation the channel sets the outputs with a predefined value...

Page 694: ...Hold off rch0_a rch0_b rch0_c rch1_a rch1_b rch1_c rch2_a rch2_b rch2_c rch5_a rch5_b rch5_c Modulation Control Bank word n word n 1 word n 2 address data allocate timer select timeout Bank Comparator...

Page 695: ...for the stored values is generated by the Modulation Control Word Bank This address generation is actually executed in a two step process since the modulation word is first addressed by the channel wh...

Page 696: ...presents the reaction module memory map Table 23 2 Signal properties Name Function RCHn_a Output pin a of reaction channel n RCHn_b Output pin b of reaction channel n RCHn_c Output pin c of reaction c...

Page 697: ...EACM Hold off Timer Bank Registers REACM_HOTBK 3 on page 23 711 0x038C 0x03FF Reserved 0x0400 0x045C REACM Threshold Bank Register REACM_THBK 24 on page 23 711 0x0460 0x05FF Reserved 0x0600 REACM ADC...

Page 698: ...de except writes to the REACM_MCR which are allowed except for the FRZ and FREN bits The global debug signal state is not changed internally while in low power mode 0 Normal Mode 1 Low Power Mode 2 FR...

Page 699: ...enables the assertion of the interrupt request to the CPU when any of the channel flags or the OVR flag are set The channel error flag bits are MAXL OCDF SCDF and TAER Note that for the interrupt to...

Page 700: ..._TCR field descriptions Field Description 0 3 Reserved should be cleared 4 15 HPRE 11 0 Hold off Timer Prescaler The HPRE 11 0 field defines the rate of the Hold off Timers on each reaction channel If...

Page 701: ...e of the Threshold Bank 1 Write received ADC result to Threshold bank address one 0 Do not write received ADC result to Threshold bank 7 WREN0 Write Enable Bit for THRADC0 The WREN0 write enable bit 0...

Page 702: ...Reaction Channel Modulation process or for capturing by the Threshold Bank Address REACM_BASE 0xC3FC_7000 0x0020 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R OVR 0 0 0 0 0 0 0 0 0 0...

Page 703: ...ed or SWMC 1 if software modulation control is selected by CHEN 11 00 Channel disabled meaning that it does not execute any modulation even if a timer window is detected or SWMC is made active In this...

Page 704: ...Enable The SQEREN bit enables the SQER flag to generate an interrupt request 1 SQER interrupt enabled 0 SQER interrupt disabled 8 RAEREN Resource Allocation Error Interrupt Enable The RAEREN bit enabl...

Page 705: ...diately used in the channel output 16 20 Reserved should be cleared 21 23 BSB 2 0 Bank Support Bits The BSB 2 0 provides control for a banked mode operation of the Reaction Module Each bit in this fie...

Page 706: ...is not active 3 MAXL ADC Maximum Limit Detection Flag The MAXL flag indicates that the ADC result which TAG is addressing this channel achieved or passed the maximum allowed limit specified in the AD...

Page 707: ...Timer Bank address is out of available range Shared Timer Bank address is out of available range Channel Input Router points to an inexistent eTPU channel and when the Hold off timer is select for bot...

Page 708: ...t if write 1 This bit is self negated thus reads always as 0 If a set event occurs at the same time a flag clear is done the set event has precedence over the clear thus the flag remains set 1 Clears...

Page 709: ...tion 0 11 Reserved should be cleared 12 15 ADCR 3 0 ADC result router field The ADCR 3 0 field selects which ADC result is used by the reaction channel for the modulation The TAG 3 0 received along wi...

Page 710: ...ank Registers REACM_HOTBK The REACM Hold off Timer Bank Registers REACM_HOTBK is a set of registers that defines the values used by the reaction channels to measure hold off time on certain modulation...

Page 711: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HOLD_OFF 11 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 23 15 REACM_HOTBK field descriptions Field Description...

Page 712: ...OLD_VALUE 15 0 Threshold Value The THRESHOLD_VALUE 15 0 unsigned value is one element of the Threshold Register register used for a threshold modulation Address REACM_BASE 0xC3FC_7000 from 0x0600 Acce...

Page 713: ...Hold off timer during appropriate times on the channel operation when this counter is not being used for the hold off modulation cycle Address REACM_BASE 0xC3FC_7000 from 0x0680 Access User read writ...

Page 714: ...12 13 14 15 R W Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MIN_PWD 11 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 23 19 REACM_MINPWD field descriptions Field Description 0 19 Reserve...

Page 715: ...ation that is executed by the channel Table 23 21 defines the modulation modes Note IOSS must not be 0b0 when MM is 0b01 threshold holdoff 5 Reserved should be cleared 6 7 SM 1 0 Sequencer Mode The SM...

Page 716: ...hreshold levels defined by THRESPT upper level threshold pointer and THRESPT 1 which corresponds to a lower level threshold pointer Output ON state is defined by HOD and Output OFF state is defined by...

Page 717: ...el is the core of the Reaction Module Each channel controls three output pins and is controlled by a Control finite state machine FSM that receives parameters to generate a modulated waveform as well...

Page 718: ...sult a PWM is generated on the output pins Note that since there are three independent outputs the PWM signal can be generated on any output or even on several outputs at the same time Usually a PWM s...

Page 719: ...odulation sequence The Modulation Control is designed to be used by all reaction channels as a centralized resource However only one channel is able to access the Modulation bank at a given time There...

Page 720: ...ere is an attempt to allocate more than three timers then an error flag TAER see Figure 23 10 is set and no timer is allocated by the requesting channel As a general guideline the system should be dim...

Page 721: ...ock diagram 23 4 4 Hold off timer bank The Hold off Timer Bank stores time values that are used by the hold off periods during the modulation process This bank is shared among all channels and is addr...

Page 722: ...the module integration An ADC result received from the on chip ADC is connected to the ADC router and then to the comparator See Figure 23 23 This result stays at the comparator input until the Reacti...

Page 723: ...ble to indicate for the selected reaction channel that a new ADC result is available It is also possible to access the ADC interface data through the REACM_SINR register NOTE The ADC interface data AD...

Page 724: ...a on each 10 clock cycles In general if n channels share the same TAG and are active at the same time the maximum supported ADC data rate is 5 n clock cycles These limitations are related to the shari...

Page 725: ...igure 23 5 for details Prescaler HPRE 11 0 is dedicated to the Hold off timers within the reaction channels Prescaler TPRE 7 0 is used by the Shared Timer Bank counters The HPRE 11 0 and TPRE 7 0 pres...

Page 726: ...CH1 will have part of its controls off even if CH1 is enabled To use BSB of CH0 in this case an option is to program channel CH0 with CHEN 11 channel enabled and with SWMC 0 modulation OFF In case of...

Page 727: ...ere can be overshoots or undershoots in the real application related to the threshold limits This occurs due to following 1 Feedback values are periodically sampled thus can present gaps on the measur...

Page 728: ...by the external timer that controls the modulation process in a worst case scenario has a minimum distance of 64 system clock periods This is required for the reaction channel state machine to proper...

Page 729: ...flag SQER is set because the SM bit field for the second modulation word is not 00 This flag occurs to indicate that the modulation was ended before the last phase of the sequence that uses the modula...

Page 730: ...e a modulation cycle had ended This is important on error conditions detected by the software thus setting the channel outputs to a safe state defined by DOFF It is important to notice that in order t...

Page 731: ...ch The glitch value for wrong operation ranges from 1 system clock to about 5 times the number of channels 23 6 Monitored modulation The modulation executed by the reaction channel can be monitored by...

Page 732: ...s at the ON state which means HOD is used to drive the outputs thus hold off functionally is not required at this moment The Hold off timer is loaded with MIN_PWD and starts counting After a time out...

Page 733: ...are too narrow and a short circuit have occurred In this case the SCDF flag is set in the CHSR Channel Status register of the corresponding channel Figure 23 10 Figure 23 33 Short circuit detection us...

Page 734: ...Hold off timer is used as the timer for the sequencer mode SM 10 In this case it is not possible to detected minimum or maximum pulse widths thus the monitored modulation is deactivated Which means t...

Page 735: ...he channel after the enable bit is asserted is defined by the MODULATION ADDR field in the channel configuration register 23 9 Reaction module interrupts The Reaction Module issues one global interrup...

Page 736: ...peration of the Reaction module SQER sequencer error occurred meaning that the timer input signal was deasserted in a modulation phase with SM 00 23 10 Use cases Figure 23 35 shows an example of the R...

Page 737: ...dically and send the digitalized results to the Reaction Module In a banked configuration as shown in this example one ADC channel is used to monitor both injectors current Note that only one channel...

Page 738: ...in this document Figure 23 37 shows a more detailed diagram of the interconnection between the injector bank and the Reaction Module Two reaction channels are used in this application CH0 is used to...

Page 739: ...ferent injectors they can share the data stored in the Modulation Word Control In this case both channels should execute the same type of Vboost Vbatt Injector A Injector B boost circuit Timer channel...

Page 740: ...propriate values in the Threshold Bank Since threshold threshold modulation is to be used in this example four pairs of values should be provided for phases A B C and D respectively Each pair correspo...

Page 741: ...up to execute a Threshold Threshold modulation but note that only I0 value is used since the phase advances when a certain current is achieved The following is a description of the bit fields in the M...

Page 742: ...typically longer compared to the other phases and defines the amount of fuel that will be injected Threshold Threshold modulation mode is used between levels I4 and I5 and Vbatt is selected as the po...

Page 743: ...ion word 0 If ADC result THRESPT the reaction channel turns the outputs off by loading LOD 2 0 to the channel outputs and advance to the next modulation cycle at time b NOTE The advance on threshold S...

Page 744: ...modulation cycle 23 10 3 Banked mode Figure 23 42 describes the interconnection of four channels controlling two injector banks Note that two output pins are not connected since the boost control is s...

Page 745: ...d accesses shared data without Host intervention Consequently for each timer event the Host CPU setup and service times are minimized or eliminated High level assembler compiler and documentation allo...

Page 746: ...a selected Time Base counter reached or exceeded a preprogrammed value Service time is the time spent servicing an event In general in microcontrollers the service time is constrained because the ins...

Page 747: ...gnals on I O pins and can also interface with external time bases through the STAC bus The eTPU engine CPU hereafter called the microengine fetches microinstructions from a Shared Code Memory SCM Shar...

Page 748: ...n SCM which may contain several Functions A Function may be assigned to several Channels but a Channel can be associated with just one Function at a given moment The association between Functions and...

Page 749: ...independently derived from the system clock or from an external input via the TCRCLK clock pin In addition the TCR2 timebase can be derived from special angle clock hardware which enables implementing...

Page 750: ...n For example a match on TCR1 can capture the value of TCR2 The channels can request service from the microengine due to recognized pin transitions input events or timebase matches The eTPU channels a...

Page 751: ...mber of parameters located in the SPRAM according to its selected Function In addition the SPRAM can be fully shared between two eTPU engines enabling direct communication between them High flexibilit...

Page 752: ...el with other microengine instructions Channel functionality is tightly integrated to the instruction set through Channel Control operations and conditional Branch operations which support jumps calls...

Page 753: ...n be replaced by system clock divided by 8 Both time bases can be exported or imported via Shared Time and Counter bus Second time base counter can work as an Angle counter enabling angle based applic...

Page 754: ...ng and ensures servicing all channels by preventing permanent blockage SPRAM shared between Host CPU and both eTPU engines supporting communication either between Channels and Host or inter channel Ha...

Page 755: ...is used for sharing real time data between multiple peripherals Contains angle clock hardware supported by microcode which can provide a 24 bit angle bus instead of time bus This feature enables the...

Page 756: ...mon to one engine but distinct between engines Error Correction support for Code SCM and Data SDM memories available on selected MCUs All changes above are upward compatible with the classic eTPU so t...

Page 757: ...software breakpoint setting On chips with a ROM SCM an internal SCM Emulation RAM may be used depending on the specific MCU implementation to replace ROM SCM for test or debug purposes SCM Emulation...

Page 758: ...th a channel The microcode may affect the logic level of an output signal1 by implementing one of two actions Specify the logic level output to the signal when there is a match or a transition Table 2...

Page 759: ...pulses that have width less then a programmed value of system clocks preventing these transitions from being input to the transition detect logic The synchronizer and digital filter are guaranteed to...

Page 760: ...their disabling forced polarity see Figure 24 37 The output disable channel groups are defined in Table 24 2 In a dual engine eTPU there are 8 output disable signals for the 64 channels 24 4 Memory m...

Page 761: ...PU 1 Extra Engine Registers 0x70 0x7F RESERVED1 0x80 0xFF RESERVED1 0x100 0x13F RESERVED 0x140 0x1FF RESERVED1 0x200 0x2FF eTPU 1 2 Global Channel Registers 0x300 0x3FF RESERVED1 0x400 0x7FF eTPU 1 Ch...

Page 762: ...TPU_TB1R_A eTPU Time Base 1 TCR1 Visibility Register on page 24 786 0x28 ETPU_TB2R_A eTPU Time Base 2 TCR2 Visibility Register on page 24 787 0x2C ETPU_REDCR_1 eTPU 1 STAC Configuration Register on pa...

Page 763: ...0x12C RESERVED 0x130 RESERVED 0x134 RESERVED 0x138 RESERVED 0x13C 0x1FF RESERVED 0x200 ETPU_CISR_1 eTPU 1 Channel Interrupt Status Register on page 24 793 0x204 RESERVED 0x208 RESERVED 0x20C RESERVED...

Page 764: ...SR_1 eTPU 1 Channel Pending Service Status Register on page 24 799 0x284 RESERVED 0x288 RESERVED 0x28C RESERVED 0x290 ETPU_CSSR_1 eTPU 1 Channel Service Status Register on page 24 799 0x294 RESERVED 0...

Page 765: ...0x9F8 RESERVED 0x9FC 0x7FFF RESERVED 0x8000 0xBFFF2 Shared Parameter RAM SPRAM 0xC000 0xFFFF2 Shared Parameter RAM SPRAM PSE mirror3 0x10000 1FFFF4 Shared Code Memory SCM5 1 This register is not impl...

Page 766: ...Enhanced Time Processing Unit eTPU2 MPC5644A Microcontroller Reference Manual Rev 6 766 Freescale Semiconductor...

Page 767: ...R 0 SDMERR WDTOA WDTOB MGE 1 MGE 2 ILF1 ILF2 SCMERR 0 0 SCMSIZE W GEC Reset 0 0 0 0 0 0 0 0 0 0 0 SCMSIZE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 SCMMISC SCMMISF SCMMISEN 0 0 VIS 0...

Page 768: ...e Global Exception was asserted is application dependent it can be coded in an SPRAM status parameter for instance This bit is cleared by writing 1 to GEC 1 Global Exception requested by microcode is...

Page 769: ...cleared 0 MISC has not yet completed an SCM signature calculation and compare since the last time SCMMISC was cleared writes are supported The value written to SCM is unpredictable if other transfer...

Page 770: ...re used 26 30 Reserved 31 GTBE Global Time Base Enable GTBE enables time bases in both engines allowing them to be started synchronously 1 time bases in both engines are enabled to run 0 time bases in...

Page 771: ...ency and wastes no microengine resources This register is used to configure and initiate CDC transfers between the parameter buffer area and the channel parameter area 1 The host asserts the STS bit t...

Page 772: ...host always reads STS as 0 1 write starts a coherent transfer 0 write does not start a coherent transfer 1 5 CTBASE 4 0 Channel Transfer Base This field concatenates with fields PARAM0 PARAM1 to deter...

Page 773: ...eats the procedure automatically 17 23 PARAM0 6 0 Channel Parameter number 0 This field in concatenation with CTBASE 4 0 determines the word address offset from the SPRAM base of the parameters that a...

Page 774: ...the thread clear channel flags disable match and transition service requests issue an interrupt or jump to an error recovery procedure Writes to unimplemented addresses do not return an error and can...

Page 775: ...usually 0xf3775ffb an instruction that clears MRLEs MRLs and TDLs disables channel service requests ends the thread and generates an illegal instruction Global Exception Figure 337 ETPU_SCMOFFDATAR R...

Page 776: ...er reset depending on the NDEDI configuration Figure 451 ETPU_ECR Register 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CDFC 0 ERBA SPP DIS 0 0 ETB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 777: ...e and a Bus Error is issued Global Channel Registers and SPRAM can be accessed normally Note Once MDIS is switched from 1 to 0 or vice versa it must not be written a different value until STF changes...

Page 778: ...15 FPSCK 2 0 Filter Prescaler Clock Control FPSCK controls the prescaling of the clocks used in digital filters for the channel input signals and TCRCLK input as shown in Table 24 10 Filtering can be...

Page 779: ...rent levels 1 Scheduler priority passing mechanism disabled 0 Scheduler priority passing mechanism enabled Note SPPDIS bit must not be changed while any channel is enabled 25 26 Reserved Table 24 9 ET...

Page 780: ...or the eTPU functions in SCM see Section 24 5 1 1 Entry points Table 24 12 shows the entry table base address options Table 24 9 ETPU_ECR field description Field Description Table 24 12 Entry table ba...

Page 781: ...is one of each of these registers for each eTPU engine NOTE Writes to this register issue bus error and are ineffective when MDIS 1 Reads are always allowed 24 4 3 1 ETPU_TBCR eTPU Time Base Configur...

Page 782: ...clock source TCR2CTL AM 0 AM 1 TCR2 Clock before prescaler Angle tooth detection 000 Gated DIV8 clock system clock 8 In this case when the external TCRCLK signal is low the DIV8 clock is blocked prev...

Page 783: ...When AM is reset non angle mode the EAC operation is disabled and its internal registers can be used as general purpose For more information see Section 24 5 7 EAC eTPU angle counter If TCR1 or TCR2...

Page 784: ...ementing speed using system clock as its clock source instead of system clock 2 1 use system clock as TCR1 clock source before the prescaler can only be set in specific combinations with TCR1CTL see T...

Page 785: ...Control TCR1 is clocked from the output of a prescaler The input to the prescaler is the internal eTPU system clock divided by 2 system clock or the output of TCRCLK filter or Peripheral Timebase inp...

Page 786: ...er or imported from STAC bus depending on the configuration set in ETPU_REDCR Figure 24 7 ETPU_TB1R Register Offset eTPU_A eTPU_Base 0x024 eTPU_B eTPU_Base 0x044 Access User read 0 1 2 3 4 5 6 7 8 9 1...

Page 787: ...ported from STAC depending on Angle Mode and STAC configurations set in registers ETPU_TBCR and ETPU_REDCR Figure 24 8 ETPU_TB2R Register Offset eTPU_A eTPU_Base 0x028 eTPU_B eTPU_Base 0x048 Access Us...

Page 788: ...tion Field Description 0 REN1 TCR1 Resource1 Client Server Operation Enable Bits This bit enables or disables Client Server operation to eTPU STAC resources REN1 enables TCR1 STAC bus operations 1 Ser...

Page 789: ...r address assigned to each TCR For a Client mode the SRV2 field determines the Server address to which the Client listens 1 Resource Server operation 0 Resource Client operation Note When TCR1 or TCR2...

Page 790: ...0 21 22 23 24 25 26 27 28 29 30 31 R WDCNT 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 24 21 ETPU_WDTR field description Field Description 0 1 WDM Watchdog Mode WDM se...

Page 791: ...ciated ETPU_IDLE register Figure 24 11 ETPU_IDLE Register Offset eTPU_A eTPU_Base 0x068 eTPU_B eTPU_Base 0x078 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R IDLE_CNT 31 16 W Reset 0 0...

Page 792: ...eTPU engine Figure 24 12 Channel registers area 24 4 6 Global channel registers The registers in this section group by type the interrupt status and enable bits from all the channels This organizatio...

Page 793: ...B eTPU_Base 0x204 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIS3 1 CIS3 0 CIS2 9 CIS2 8 CIS2 7 CIS2 6 CIS2 5 CIS2 4 CIS2 3 CIS2 2 CIS2 1 CIS2 0 CIS1 9 CIS1 8 CIS1 7 CIS1 6 W CIC3...

Page 794: ...C 21 DTR C 20 DTR C 19 DTR C 18 DTR C 17 DTR C 16 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DTR S 15 DTR S 14 DTR S 13 DTR S 12 DTR S 11 DTR S 10 DTR S 9...

Page 795: ...20 21 22 23 24 25 26 27 28 29 30 31 R CIOS 15 CIOS 14 CIOS 13 CIOS 12 CIOS 11 CIOS 10 CIOS 9 CIOS 8 CIOS 7 CIOS 6 CIOS 5 CIOS 4 CIOS 3 CIOS 2 CIOS 1 CIOS 0 W CIOC 15 CIOC 14 CIOC 13 CIO C 12 CIO C 11...

Page 796: ...DTR OC 27 DTR OC 26 DTR OC 25 DTR OC 24 DTR OC 23 DTR OC 22 DTR OC 21 DTR OC 20 DTR OC 19 DTR OC 18 DTR OC 17 DTR OC 16 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 797: ...se 0x244 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIE 31 CIE 30 CIE 29 CIE 28 CIE 27 CIE 26 CIE 25 CIE 24 CIE 23 CIE 22 CIE 21 CIE 20 CIE 19 CIE 18 CIE 17 CIE 16 W Reset 0 0 0 0...

Page 798: ...4 5 6 7 8 9 10 11 12 13 14 15 R DTR E 31 DTR E 30 DTR E 29 DTR E 28 DTR E 27 DTR E 26 DTR E 25 DTR E 24 DTR E 23 DTR E 22 DTR E 21 DTR E 20 DTR E 19 DTR E 18 DTR E 17 DTR E 16 W Reset 0 0 0 0 0 0 0 0...

Page 799: ...r read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SR31 SR30 SR29 SR2 8 SR2 7 SR2 6 SR2 5 SR2 4 SR23 SR22 SR2 1 SR2 0 SR1 9 SR1 8 SR1 7 SR1 6 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 2...

Page 800: ...S24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SS15 SS14 SS13 SS12 SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1...

Page 801: ...l registers of each eTPU engine as shown in Table 24 32 There are 64 structures defined one for each available channel in the eTPU System 32 for each engine The base address for the structure presente...

Page 802: ...icrocontroller Reference Manual Rev 6 802 Freescale Semiconductor Channel_Register_Base ETPU_Engine_Channel_Base channel_number 0x10 where ETPU_Engine_Channel_Base ETPU_Base 0x400 for Engine 1 ETPU_En...

Page 803: ...on Field Description 31 CIE Channel Interrupt Enable This bit is mirrored from ETPU_CIER see Section 24 4 6 5 ETPU_CIER eTPU Channel Interrupt Enable Register 1 Enable interrupt for this channel 0 Dis...

Page 804: ...ETCS CFS and CPBA must only be changed while the channel is disabled field CPR 00 8 10 Reserved 11 15 CFS 4 0 Channel Function Select This field defines the function to be performed by the channel see...

Page 805: ...host byte address for channel x 2 parameter granularity see Section 24 5 2 4 SPRAM organization As seen by the Host the channel parameter base byte address is without parameter sign extension ETPU_Ba...

Page 806: ...CIC CIOC DTR C DTR OC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IPS OPS OBE 0 0 0 0 0 0 0 0 0 0 0 FM W Reset 0 11 1 The IPS value after reset is MCU depen...

Page 807: ...Status 1 data transfer request overflow asserted for this channel data transfer request overflow negated for this channel 9 DTROC Data Transfer Request Overflow Clear 1 clear status bit keep status b...

Page 808: ...output buffer enable signal controlled by microcode 19 29 Reserved 30 31 FM 1 0 Channel Function Mode1 Each function uses this field for specific configuration These bits can be tested by microengine...

Page 809: ...Unimplemented or Reserved Table 24 35 ETPU_CxHSRR field description Field Description 0 28 Reserved 29 31 HSR 2 0 Host Service Request This field is used by the Host CPU to request service to the cha...

Page 810: ...number of entry points available Each engine can be controlled by up to 32 Functions at a time A Function can be assigned to several channels but only one Function can be assigned to a given Channel a...

Page 811: ...more than one combination having its Entry Point repeated in the table Each 32 bit word in the Entry Table holds two Entry Points Note that the Entry Table can be placed in any SCM address multiple of...

Page 812: ...ons field C 4 0 according to one of two encoding schemes Standard Entry Table Condition encoding scheme shown in Table 24 36 which privileges Host Service Requests Alternate Entry Table Condition enco...

Page 813: ...Section 24 5 5 1 2 Pin Control Registers The MatchB TransA column refers to the recognition of either a Match event specified by MatchB channel register or the detection of a channel input signal even...

Page 814: ...ble 24 36 Standard channel condition encoding scheme No Encoded channel condition s C4 C0 Host service request bits Link request MatchA TransB Match 2 TransA In Output pin state1 Channel flag1 Channel...

Page 815: ...for better state decoding making this scheme better suited for Functions which need more states and or faster state decoding without needing many HSRs 21 10101 000 0 1 1 0 x 1 22 10110 000 0 1 1 1 x 0...

Page 816: ...2 00010 01x x x x 1 x 0 3 00011 01x x x x 1 x 1 4 00100 10x 001 x x x x x x 5 00101 11x x x x x x x 6 00110 000 1 0 0 0 x x 7 00111 000 1 0 0 1 x x 8 01000 000 x 1 0 0 0 0 9 01001 000 x 1 0 0 0 1 10 0...

Page 817: ...11011 000 x 1 1 0 1 1 28 11100 000 x 1 1 1 0 0 29 11101 000 x 1 1 1 0 1 30 11110 000 x 1 1 1 1 0 31 11111 000 x 1 1 1 1 1 Host Service Request 1 The ETPU_CxCR bit ETPD selects between input and outpu...

Page 818: ...read execution If they are disabled a match recognition can only occur after channel service For more details refer to Section 24 5 5 2 Match Recognition Matches are disabled during the thread Matches...

Page 819: ...5 4 Parameter sharing and coherency No instructions are executed at the engine where the time slot transition period occurs but the other engine can execute normally Match A B is unconditionally disa...

Page 820: ...PRAM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB END Y Entry Addr Y1st Inst Addr Entry Point Y 1st Inst CHANNEL X CHANNEL Y X END TST1 TST2 TST3 Y 3rd Inst Preload P DIOBPP 1 Pentry point PP T...

Page 821: ...nal ERTA ERTB Preload HSR sampled for Flags for Entry Point PC INST SPRAM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB Entry Point and Branch Condition END Y Entry Addr Y1st Inst Addr Entry Poi...

Page 822: ...5 9 4 1 Ending current thread END A forced END by host writing to the ETPU_ECR bit FEND see Section 24 4 2 5 ETPU_ECR eTPU Engine Configuration Register A forced END caused by Watchdog timeout see Sec...

Page 823: ...er another keeps the count running The counter is also reinitialized when a thread is forced to end so that a new count begins if another TST initiates at the following microcycle The following applie...

Page 824: ...uped by Channel and grouped by type interrupt status interrupt enable data transfer status data transfer enable This allows either channel oriented or bundled channel Host interrupt service schemes or...

Page 825: ...ed The same mechanism and respective registers ETPU_CDTROSR are available for Data Transfer Requests If interrupt is set and cleared at the same time set prevails and overflow is not altered keeps the...

Page 826: ...peated in the 8 most significant bits of the read value on all 32 bit reads and most significant 16 and 8 bit reads The same parameters written in the standard SPRAM address space are read from the PS...

Page 827: ...CPBA 0x014 ETPU_C1CR CPBA 0x018 ETPU_C2CR CPBA 0x168 ETPU_C3CR CPBA 0x172 ETPU_C30CR CPBA 0x180 ETPU_C31CR CPBA 0x16E ETPU2 Channel 3 Parameters ETPU2 Channel 0 Parameters ETPU1 Channel 0 Parameters E...

Page 828: ...ay is write HSR 0 only when HSR 0 Error recovery or emergency host procedures may require one to the safely abort service and reset channel state when an HSR is already pending or executing In these c...

Page 829: ...interrupt jump to an error recovery procedure1 Writes to unimplemented addresses do not return error and can write on unspecified mirror addresses so they should be avoided 24 5 3 Scheduler Every Fun...

Page 830: ...the transition will occur even after the channel is disabled Service requests previously pending or that occur while a channel is disabled remain asserted while the channel is disabled and are servic...

Page 831: ...ot has a fixed priority level that the Scheduler honors first Divided into sets of seven time slots are numbered from one to seven Figure 24 31 illustrates the numbered time slots in sets of seven fie...

Page 832: ...e shown in Figure 24 32 Each cycle contains seven time slots or less if no service request exist In cycle B no high level or middle level service requests are present before time slot three which is a...

Page 833: ...until a time slot that matches the priority of one of the requesting channel s The time slot advance takes no extra clocks If no channel requests service the time slot counter stays at time slot 1 The...

Page 834: ...e requests The Scheduler services channels on each of the three priority levels beginning with the lowest numbered channel on that level 24 5 3 2 4 Priority scheme example The overall priority scheme...

Page 835: ...ted have been allocated execution time Under this condition all service grant bits of the high level serviced channels are negated The Scheduler proceeds to time slot four 7 Time slot four is allocate...

Page 836: ...ffers in SPRAM to their definitive locations or vice versa These methods have the disadvantage of wasting processing and code memory resources eTPU also provides a Coherent Dual parameter Controller C...

Page 837: ...ine dual parameter atomicity Microengine has the ability to access two parameters coherently in back to back accesses at random addresses once it accesses SPRAM it has priority over Host for another a...

Page 838: ...in the channel area may be shared by channels on them both During CDC operation the Host may suffer from 3 up to 11 system clocks wait states1 and the Microengine s may suffer up to 2 microcycle wait...

Page 839: ...nnels in different engines and for engine to engine synchronization Semaphores are also the only way to ensure coherent access to parameters shared between the two Microengines Attempting to lock one...

Page 840: ...microengine is arbitrating for the access of its second parameter in a back to back access1 All pairs of back to back parameter accesses are coherent with respect to Host and CDC not to the other mic...

Page 841: ...channel to request service configuring a Match Service Request eTPU uses two kinds of comparator to assert a Match Event an Equal comparator in which both the Match Register and the value of the selec...

Page 842: ...citly request service from another channel through the microengine LINK Register A microcode write to the LINK Register asserts a service request to the channel whose number matches the contents of LI...

Page 843: ...c 2 Trans B Match B OPACB IPACB EDF Output FF Output Logic Set Rst OBE FF ucode TBSA 2 0 PDCM SRI SRI ucode MTD Rst Set ucode PDCM ucode IPACA ucode IPACB ucode OPACA ucode OPACB Output Signal Output...

Page 844: ...registers from only one channel at a time The Channel Selection CHAN register see Section Channel Selection Register CHAN accessible only by microcode defines the channel whose registers are being ac...

Page 845: ...ERTA and ERTB therefore becoming visible to the microcode At the same time updated values of MRLA MRLB TDLA and TDLB are sampled into the branch logic making the register values and the flags coherent...

Page 846: ...e copied into ERTA B microengine registers For more information see Section 24 5 5 3 Transition Detection and Time Base Capture TBSA and TBSB Time Base Selection Registers TBSA B are 3 bit registers w...

Page 847: ...tion 24 5 5 2 1 MRLA B Match Recognition Latches MRLEA B Match Recognition Latch Enable See Section 24 5 5 2 3 MRLEA B Match Recognition Latch Enable TDLA B Transition Detection Latch See Section 24 5...

Page 848: ...ate of the input signal at the occurrence of the corresponding Match Match A used for IPACA Match B used for IPACB PSTI flag test on branch no no BCC 0 PSTO flag test on branch write no immediate BCC...

Page 849: ...ecognitions or transition detections the pin control logic sets PSTO value according to the event number Match A Transition A or Match B Transition B and the contents of OPACA IPACA or OPACB IPACB reg...

Page 850: ...e request sources are cleared and until a new service request rises The channel PRSS flag is sampled into the branch logic as the PRSS flag see Table 24 113 during the time slot transition period or w...

Page 851: ...re unique per channel Table 24 47 summarizes the registers and access options DIGITAL FILTER Q D CHAN Transition Q S R from output logic to branch logic PSTO PSS to branch logic PSTI Input Pad PSTI Q...

Page 852: ...HAN register is written accesses are qualified by the new CHAN register value from the instruction following CHAN assignment on except CaptureA B sampling into ERTA B and Match register writing from E...

Page 853: ...lso used to select the User Programmable Channel Mode If this selection is made the channel behavior is defined by the settings of the UDCM register see Section UDCM User Defined Channel Mode Branch u...

Page 854: ...Service Request Inhibit Latch SRI blocks channel service requests due to the assertion of MRLA B and or TDLA B SRI does not affect recognition of Link Service Requests or Host Service Requests neithe...

Page 855: ...vent is qualified by a set of match enabling conditions to the Match Recognition Registers MRLA B To recognize the match and assert these registers the following match enabling conditions are required...

Page 856: ...nel mode In some double match blocking channel modes Match A B event blocks the occurrence of Match B A in a first win scheme It is the transition from 0 to 1 in MRL that causes the Match actions apar...

Page 857: ...etting overrides the MRLE negation conditions due to channel logic or microcode see Section 24 5 5 4 Channel Modes By combining write to Match A B with MRLEA B negation microinstructions the microcode...

Page 858: ...y with the assertion see Section 24 7 1 Microcycle and I O timing 1 MRLA B and TDLA may depending on the channel mode inhibit the capture of the second event s TCR into CaptureA B As a general rule va...

Page 859: ...0 to 1 in TDL that causes the Transition actions even if TDL assert conditions are satisfied no action due to a Transition occurs if TDL was already set to 1 However if a Transition and a microoperat...

Page 860: ...to conditions for event blocking enabling capture and service requests Signals MSR TSR MCAP TCAP M1ET M1EM2 M1BM2 M2BM1 M2BT T1BM1 T2BM1 TBM2 and T1ET2 are decoded from programmed channel mode PDCM i...

Page 861: ...vice Request on the 1st1 Transition 1 Transition A captures corresponding Time Base Transition B captures corresponding Time Base issue Service Request on the 2nd3 Transition 3 2nd Transition means th...

Page 862: ...A always blocks Match A Match B always blocks Match B Table 24 55 Predefined channel mode control signals decoding Predefined mode MSR MCAP M1ET M1EM2 M1BM2 M2BM1 M2BT T1BM1 T2BM1 TBM21 T1ET2 TSR1 1...

Page 863: ...anced Time Processing Unit eTPU2 MPC5644A Microcontroller Reference Manual Rev 6 Freescale Semiconductor 863 3 sm_st_e is an exception in the capture scheme See Section Single match enhanced mode sm_s...

Page 864: ...2 Match A SR Match B SR TransA SR TransB SR MSR 1 MSR 0 MSR 0 MSR 1 TCAP CaptureB MCAP NOTE all flip flops but MRLE reset dominant load enable CaptureA MCAP load enable sm_st_e MEF Channel Service Non...

Page 865: ...d mode when UDCM bit T1ET2 0 Matches are generally not ordered except on specific ordered match modes m2_o_st and m2_o_dt Match capture s never overrides a Transition capture while Transition captures...

Page 866: ...MRLA and MRLB are set before the mutual blocking takes effect Figure 24 40 Either Match Blocking Modes em_b_st em_b_dt S R Q TDLA T2 S R Q MRLA T2 T4S R Q MRLEA sysclk Comparator A ucode ERWA SRI Tra...

Page 867: ...cking Modes em_nb_st em_nb_dt S R Q TDLA T2 S R Q MRLA T2 T4S R Q MRLEA sysclk Comparator A ucode ERWA SRI Trans Event A S R Q TDLB T2 S R Q MRLB T2 T4S R Q MRLEB sysclk Comparator B ucode ERWB ucode...

Page 868: ...atch Request Modes bm_st bm_dt In these modes match service request is generated only after both match recognitions occurred By definition this is a non blocking match mode match recognitions do not b...

Page 869: ...sserts MRLA and enables Match B and transitions Match B asserts MRLB generates a match service request and blocks both transitions S R Q TDLA T2 S R Q MRLA T2 T4S R Q MRLEA sysclk Comparator A ucode E...

Page 870: ...0 Double Trans S R Q TDLA T2 S R Q MRLA T2 T4S R Q MRLEA sysclk Comparator A ucode ERWA SRI Trans Event A S R Q TDLB T2 S R Q MRLB T2 T4S R Q MRLEB sysclk Comparator B ucode ERWB ucode TDL Trans Even...

Page 871: ...Trans Event A S R Q TDLB T2 T4S R Q MRLEB sysclk ucode ERWB ucode TDL Trans Event B ucode MRLA Match A SR Match B SR TransA SR TransB SR CaptureB load enable CaptureA load enable Double Trans Double...

Page 872: ...onality of sm_st captures both time bases at once due to a match recognition Figure 24 46 Single match enhanced mode sm_st_e S R Q TDLA T2 S R Q MRLA T2 T4S R Q MRLEA sysclk Comparator A ucode ERWA SR...

Page 873: ...ng Double Transition em_b_dt In double transition mode each transition is related to one match recognition TDLA assertion captures its related timebase blocks Match A and enables TDLB TDLB assertion b...

Page 874: ...ion opens the window and enables transition detection on TDLA from this time on MRLB assertion blocks Match A by negating MRLEA providing conditional window opening because transitions are indirectly...

Page 875: ...red to generate a match service request The second transition detection asserts TDLB blocks Match A and Match B captures its related timebase and generates transition service request In this mode a Ma...

Page 876: ...ed Mode sm_st_e This is an enhanced single transition and single match channel mode which provides timing information of the digital filter delay The CaptureA register captures the timebase selected b...

Page 877: ...th single double match as explained in the following subsections Either Match Blocking Modes em_b_st em_b_dt On an output signal these modes are useful when using two different time bases to set a req...

Page 878: ...ice request is generated after both conditions are met This mechanism can set two conditions to do a required pin action and the first recognition changes the signal but service is called only after b...

Page 879: ...output pin action occurs that is a match on the action logic with OPAC 000 inhibits simultaneous actions of the other OPAC if prevailing according to Table 24 56 That also applies when output actions...

Page 880: ...es Match B A rising edge on input sets output high On Match B the window closes and input signal is checked if sampled high the output resets otherwise it stays high In the third example a pulse is ge...

Page 881: ...atch A Match B Input signal Output signal IPACA 100 OPACA 100 MatchA window open time input sampling IPACB 000 OPACB 001 MatchB window close time MatchA pulse width PDCM em_nb_dt Example 2 Pulse gener...

Page 882: ...they always access the serviced channel LINK and LSR regardless of the value written in CHAN If microcode executes an instruction with field LSR 0 clear Link Service Request the link branch condition...

Page 883: ...same value the input signal state is updated Note that when the FPSCK field selects the system clock divided by two the EDF works like the TPU1 four clock digital filter 24 5 5 6 2 Three Sample Mode I...

Page 884: ...k rate for the filter signal to define wider valid pulses and filter out wider noise pulses The filter prescaler clock control is a division of the system clock To guarantee pulse detection by the dig...

Page 885: ...ue ETPU_TBCR bit TCR1CS is 0 see Section 24 4 3 1 ETPU_TBCR eTPU Time Base Configuration Register the Enhanced Digital Filter is not configured as bypass see Section 24 5 5 6 Enhanced Digital Filter E...

Page 886: ...rotocol and definition of STAC modules refer to IPI STAC and Section 24 5 6 3 STAC Interface The TCR2 counters between the two engines are out of phase by 1 system clock even when Time Bases are share...

Page 887: ...gtbe_in 1 the prescaler starts a new count and the new TCR1P becomes effective When TCR1 is written by microcode the prescaler is reloaded with TCR1P and it becomes effective if etpu_gtbe_in is assert...

Page 888: ...diagram for TCR2 clock control When TCR2 is not driven by the EAC or STAC the ETPU_TBCR field TCR2CTL selects the clock source also allowing TCR2 to be frozen independently of TCR1 see Section 24 4 3...

Page 889: ...p to TCR2P when etpu_gtbe_in is asserted When TCR2 increments etpu_gtbe_in 1 the prescaler starts a new count and the new TCR2P becomes effective When TCR2 is written by microcode the prescaler is rel...

Page 890: ...ower than eight system clocks 24 5 6 2 6 TCR2 bus in angle clock mode In this mode the TCR2 counter operates as part of the eTPU Angle Counter EAC The TCR2 bus value reflects this angle representation...

Page 891: ...le counter Proper configuration of the following bits is necessary to determine what can drive the STAC bus ETPU_TBCR AM and ETPU_REDCR REN2 RSC2 according to Table 24 59 Note that Angle Mode is not a...

Page 892: ...ts etpu_gtbe_out and etpu_gtbe_in enables time bases to start The etpu_gtbe_out signal can be used by MCU integration for synchronization between eTPU time bases and time bases from other modules If t...

Page 893: ...s the channel filters see Table 24 15 The TCRCLK filter delay and prescaling determines the minimum detectable TCRCLK pulse widths and therefore its maximum frequency as shown in Section 24 5 5 6 5 Fi...

Page 894: ...ds the channel Channel 0 1 or 2 generates the signal transition service request and can also be used for generation of a window filter on this transition to qualify TCR2 clocks For this purpose the se...

Page 895: ...D TPR 10 TICK S W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Field Description 9 0 TICKS Angle Ticks Number in the Current Tooth This field defines the number of angle ticks in the current physical tooth...

Page 896: ...sing Tooth Counter Decremented on each estimated tooth stops at zero Used for generation of Dummy Tooth whenever it holds a non zero value 00No missing tooth 01One missing tooth 10Two missing teeth 11...

Page 897: ...ts of TCR1 clocks as system clocks divided by 2 TCR1P 1 even if TCR1CS 1 see Section 24 4 3 1 ETPU_TBCR eTPU Time Base Configuration Register Refer to Section 24 5 7 4 1 Calculating the angle tick per...

Page 898: ...igure 24 55 EAC PLL FILTER TCR1 clock divided by TRR TICK COUNTER MICROCODE Estimated Tooth Time New TRR Tick clock TCR1 clock PHYSICAL TOOTH CAPTURED TCR1 TICKS TOOTH TICKS TCR2 TIME EAC CHANNEL CAPT...

Page 899: ...om Channel 0 in Angle Mode Angle Mode Tooth Program Register 24 Integer Fraction Fraction Accumulator 9 9 Carry 9 Tick Prescaler 15 Angle Tick TCR1 Clock Hold Din 24 10 24 Angle Tick Generator Angle C...

Page 900: ...nels or external STAC clients if TCR2 is a STAC server which compare angle in equal mode These peripherals must get all the valid angle values in a sequential manner to avoid missing angle matches TCR...

Page 901: ...be represented with 24 bits Using shift left nine positions and one divide operation would get the result in MACL register in MDU which holds the integer and nine bits of the fraction Angle_Tick_Rate...

Page 902: ...s provides accuracy of two LSB on a full scale TICKS 1023 or one LSB on lower scale TICKS 511 When the Tick Prescaler gets High Rate mode indication from the Angle Counter Logic it generates angle tic...

Page 903: ...l may be programmed with a slow and reliable digital filter and get accurate time measurement of the digital filter delay To assert the end of the estimated tooth period the Count Control and High Rat...

Page 904: ...period and updates TRR This operation slows the angle tick rate generated by the Angle Tick Generator on the fly to the rate required for the new tooth period Since the microcode service is initiated...

Page 905: ...ode using the most updated TRR value as input to the Angle Tick Generator The logic samples the updated TICKS value for the tooth estimation last tooth indication and number of missing teeth from TPR...

Page 906: ...the end time of the current physical tooth For correct operation this field should be updated before the Tooth Tick Counter has reached either the old or the new TICKS value During High Rate mode ope...

Page 907: ...ing a new period of the engine cycle This implementation provides an engine cycle based periodic angle measurement 24 5 7 6 2 Handling missing teeth The EAC can handle up to three missing teeth in two...

Page 908: ...n the EAC switches to High Rate mode in order to run through all the valid angle values including the dummy teeth When the Tooth Tick Counter reaches the TICKS value on High Rate mode and the dummy to...

Page 909: ...extreme deceleration The microcode can assert the IPH bit in TPR to force the detection of the missed physical tooth It can also calculate the accumulated angle bus error and fix the next estimated to...

Page 910: ...ble transition modes On mode m2_st the window opens on Match A which enables Transition A and does not close with Match B If Match B comes before Match A it blocks Match A and hence Transition A On mo...

Page 911: ...nd write behaves as if EAC is still in Normal mode Only in the next microcycle after execution of a NOP for instance the TPR writes are buffered acknowledging High Rate mode MISSCNT and LAST can be wr...

Page 912: ...24 5 7 12 5 IPH and HOLD If IPH and HOLD are asserted at once IPH cancels the HOLD and both reset The EAC is not frozen regardless of the mode 24 5 7 12 6 LAST and HOLD If LAST and HOLD are written 1...

Page 913: ...TPR TRR registers are accessible by microcode 24 bit ALU and Post ALU shifter performs basic arithmetic and logical operations described in Section 24 5 8 2 ALU and Post ALU Shifter MDU MAC Divide Un...

Page 914: ...ic 4 24 24 24 24 24 24 eTPU CHANNELS ER1 Bus ER2 Bus 24 SPRAM A Bus 24 24 24 32 24 1 MACH MACL MAC 24 24 24 DIVIDE UNIT 24 AIN N V Z C MB Flags to to Branch Logic MN MV MZ MC 5 RAR Channels TCRs Micro...

Page 915: ...tion 24 5 9 1 SPRAM microoperations P is automatically loaded with one parameter before the thread starts parameter preload For more information see Section 24 5 1 1 5 Entry point format and Section 2...

Page 916: ...nd Post ALU Shifter allowing the SR to be used to perform 48 bit shift right see Section 24 5 9 2 6 Shift operations 24 5 8 1 5 MACH and MACL Registers Both MACH and MACL are 24 bit registers part of...

Page 917: ...r example to add and shift using only one microinstruction In some microinstruction formats it is not possible to specify the operation executed by ALU In these cases ALU will always perform addition...

Page 918: ...arry Flag represent the sign of ALU s result considering operation size Carry Flag equal to 0 means a negative result Carry Flag definition is operation dependent The Carry flag in add subtraction wit...

Page 919: ...more details Table 24 63 describes how CIN and BINV fields change ADD operation behavior ALU adder output can be 1 bit shifted or 1 bit rotated right as follows Shift right if BINV 1 result 23 0 adder...

Page 920: ...4 bits T4BBS A 24 bits T2ABD B 24 bits and ALUOP Add ROR then B gets A P with bits 7 0 rotated even though the operation size is 24 bits Table 24 64 describes Carry flag behavior Table 24 64 Carry fla...

Page 921: ...ld is ignored and BINV field inverts bitwise NOT BS C and V Flags are never updated on these operations Table 24 66 Describes AND OR and XOR bitwise operations 0 8 bits rotate right adder carry from b...

Page 922: ...0 result AS 1 31 BS 4 0 clear bit BINV 0 result AS 1 31 BS 4 0 24 5 8 2 6 Exchange bit Exchange the AS bit determined by BS 4 0 with C flag If the bit number resolves to a value greater than 23 no exc...

Page 923: ...ield On this operation AS is interpreted as a signed number and its absolute value is the result V and N flags are updated with the result signal determined by the operation size AS bit 23 after size...

Page 924: ...ng operation terminate immediately and is left incomplete When selecting an operation that uses MDU the result is always placed in MACH and MACL registers and the register selected as destination does...

Page 925: ...It is also allowed to mix different sizes in multiply mac sequences Multiply accumulate operations are similar to multiply operations except that the contents of MACH and MACL registers are added to t...

Page 926: ...MC is set if result can not be represented by a 48 bit unsigned non negative number MACU never resets MC flag MC flag is left as is if no carry occurs or set otherwise This allows checking the carry f...

Page 927: ...Unsigned Divide div At the end of a divide operation MACL holds the result of the division taking A source as numerator and B source as denominator while MACH holds the remainder If a divide by 0 is e...

Page 928: ...ues in MDU and ALU flags are not initialized ALU flags are described in Section 24 5 8 2 1 ALU Flags MDU flags are described in Section 24 5 8 3 10 MDU Flags MDU and ALU flags are updated during execu...

Page 929: ...veral in one group Complete microinstruction formats are shown in Section 24 5 9 7 Microinstruction formats Parallelism conflicts may arise when two operations are executed in the same microinstructio...

Page 930: ...mode the address range is 256 parameters addressed by field AID which in this mode is 8 bit wide These parameters are located in SPRAM addresses from 0 to 255 physical_address AID 7 0 Selected channe...

Page 931: ...available in microinstructions that support SPRAM access the source destination is P 24 5 9 1 3 SPRAM operation size When using DIOB register to perform SPRAM data transfers the operation size is alwa...

Page 932: ...B operations see Section 24 5 9 1 6 DIOB stack operation and ALU operations are resolved like a normal SPRAM operation see Table 24 117 24 5 9 1 6 DIOB stack operation SPRAM Indirect Addressing Mode s...

Page 933: ...s where there is no operation selection field ALUOP ALUOPI or SHF the operation performed is always addition however it is possible to perform subtraction increment or decrement using fields BINV see...

Page 934: ...and results are stored in MACH and MACL see Section 24 5 8 3 MAC and Divide Unit MDU ABSE and ABDE are not available in some microinstruction formats that support ALU MDU operations However in all for...

Page 935: ...ABDE Meaning in microinstruction formats without ABSE ABDE1 1 T4BBS also selects A source and destination register set in this case according to Table 24 79 000 BS 23 0 P 23 0 001 BS 23 0 A 23 0 010...

Page 936: ...SR 23 0 AD 23 0 24 LINK 7 0 AD 7 0 8 0010 ERTA 23 0 AD 23 0 1 1 T2ABD 0010 with first register set also writes to MatchA or UDCM registers of the selected channel if field ERWA 0 see Section 24 5 9 3...

Page 937: ...nts a parameter address CPBA 2 can be used as A source using T4ABS 1010 when T4ABS selects a source from the second register set In this case CHAN_BASE is loaded into AS 13 2 to form the byte address...

Page 938: ...r determined by the operation size When neither CCS nor CCSV are present in the microinstruction flags are not sampled CCS and CCSV do not affect the Carry update on Exchange Bit operation see Section...

Page 939: ...on for CIN and BINV fields when max constant is selected the carry in is 0 and B source max constant itself is not inverted neither the carry out Max constant is the value which added to a time base v...

Page 940: ...post ALU shift operation using ALUOP field ALU will always add the sources before shifting the result Carry flag is only updated when CCS or CCSV 1 0 fields allow it see Section 24 5 9 2 3 Flags samp...

Page 941: ...e not updated MDU does not start any operation i e MACH and MACL are not updated SR does not shift T4ABS selected read match does not occur 24 5 9 2 8 A Source size override Some values if the AS CE f...

Page 942: ...aken from the size overridden value not the original one A source sign is not extended in microinstructions without SEXT field even if AS CE field is present 24 5 9 2 10 ALU MDU Operation Selection Wh...

Page 943: ...AS BS arithmetic addition 10101 AS BS shl 1 arithmetic addition with 1 bit post ALU shift left Section Post ALU shift operations 10110 AS BS shr 1 arithmetic addition with 1 bit post ALU shift right S...

Page 944: ...with immediate data Enhanced operations with immediate data selected by ALUOPI 5 bits are allowed only with an 8 bit immediate operand see Table 24 96 2 In setb and clrb operations the register that...

Page 945: ...m8 AD 15 0 0x0 bitwise AND with clear 10100 AS imm8 arithmetic addition 10101 AS imm8 shl 1 arithmetic addition with 1 bit shift left 10110 AS imm8 shr 1 arithmetic addition with 1 bit shift right 101...

Page 946: ...tate decoding For more details see Section 24 5 1 1 Entry points 24 5 9 3 2 Comparator and time base selection TBSA and TBSB fields 4 bit wide each are used to configure the type of the comparator and...

Page 947: ...A B during Time Slot Transition See Section 24 5 5 2 Match Recognition 24 5 9 3 4 Immediate pin state control It is possible to change output signal state immediately by using PSC 2 bits and PSCS 1 bi...

Page 948: ...s indicate the state of matches and transitions detected in the selected channel and it is possible to clear those flags using the microcode fields MRLA MRLB 1 bit each and TDL 1 or 2 bits depending o...

Page 949: ...UDCM Registers Some instruction formats have a two bit MRLE field see Section 24 5 9 7 Microinstruction formats which allows independent disabling of Matches 1 and 2 as shown in Table 24 106 Table 24...

Page 950: ...ouble Transition PDCM 0 1 predefined modes PDCM is also used to select the user defined channel mode defined by the channel register UDCM see Section UDCM User Defined Channel Mode Table 24 107 Disabl...

Page 951: ...spatch call that can be used to implement a jump table In call or dispatch call microoperation the return address is saved in the RAR If nested sub routine calls are necessary return address values ha...

Page 952: ...ll microoperations is that when a call is executed the value of PC or PC 1 depending on flush see Section 24 5 9 4 5 Flush pipeline is saved in the RAR The microcode field J C 1 bit selects whether ju...

Page 953: ...100101 MN MDU flag 110101 P 25 100110 MC MDU flag 110110 P 26 100111 MZ MDU flag 110111 P 27 101000 TDLA channel flag 111000 P 28 101001 TDLB channel flag 111001 P 29 101010 MRLA channel flag 111010...

Page 954: ...OP if the branch is taken If FLS 1 the microinstruction placed after the branch is executed either if the branch is taken or not as shown in Figure 24 63 Flush also controls which value is stored in R...

Page 955: ...chieved through any of the formats shown on Section Table 24 118 Microinstruction Formats where the user can assign to each individual field the corresponding value for No Operation However to prevent...

Page 956: ...specified as destination for both ALU and SPRAM microoperations In this case the value loaded into P or DIOB is the one read from SPRAM However the ALU operation is executed and its flags are updated...

Page 957: ...E 24 5 9 6 5 CHAN assignment Read Match and ERWA B When CHAN is a destination of an ALU operation it causes a read of the CaptureA B register values into ERTA B The Capture registers loaded into ERTA...

Page 958: ...ec DIOB 15 2 DIOB write with posinc value written is before increment 24 5 9 6 8 SRC and ALU MDU operations If operation SRC is active field SRC 0 and register SR is selected as destination of an ALU...

Page 959: ...Enhanced Time Processing Unit eTPU2 MPC5644A Microcontroller Reference Manual Rev 6 Freescale Semiconductor 959 24 5 9 7 Microinstruction formats See Table 24 118...

Page 960: ...B2 1 ZRO AID 6 0 channel param B3 0 0 0 STC AB SE AB DE rsv 1 1 B4 0 0 1 0 CCSV 1 AS CE ALUOP B5 FL 0 SEXT SMPR B6 1 rsv SRC AB SE AB DE B7 0 1 1 END SHF TDL PSC MRLA ERWA MRLB ERWB ABSE ABDE CCS MRLE...

Page 961: ...3 FL 10 rsv SMPR E4 0 11 1 rsv F1 rsv 1 rsv 111 rsv format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALU Operations Channel Control Config Operations RAM Op...

Page 962: ...nt request from other blocks or outside MCU NDEDI is an IP block designed to support Nexus functionality for the eTPU When Internal Debug Interface is connected to an NDEDI block the MCU can provide N...

Page 963: ...is ignored while VIS 1 MDU continues executing until it finishes any ongoing operation even if microengine is in halt state except when the halted instruction is an END There are two kinds of halt sta...

Page 964: ...icroinstruction execution or if in halt_exec in single step see Section 24 5 10 2 6 Single step execution There are situations when requests for stopping an engine breakpoint and service can occur sim...

Page 965: ...efore the halt state is suspended if the original program flow must be followed the original instruction at the HALT address must be executed regardless if the software breakpoint is removed replacing...

Page 966: ...alt state by the forced execution of a branch with flush see Section 24 5 10 2 7 Forced microinstruction execution making single step execute a NOP instead of the next instruction in the program flow...

Page 967: ...set options are limited by the possibilities of forced microinstruction execution If the eTPU runs not single stepping after exiting the halted state the conditions modified during halt may remain onl...

Page 968: ...on Register The average time for a MISC calculation can be measured by checking SCMMISC state at regular intervals incrementing a counter and clearing SCMMISC if it is set MISC accesses to the SCM arr...

Page 969: ...SCM is implemented in RAM it should be initialized with the eTPU application code prior to configuring the eTPU Configuration procedures are summarized as follows If SCM is implemented as RAM load th...

Page 970: ...assume their reset values NOTE All eTPU input clocks must pulse during reset so that both engines are reset even if they are in Module Disable or Stop mode 24 6 2 2 Software reset eTPU has no Software...

Page 971: ...wever it has bigger average latency because the Transfer Service thread has to contend for a time slot to execute This latency can be minimized if Transfer Service thread is assigned to a separate cha...

Page 972: ...e thread will complete execution possibly issuing an interrupt or DMA request before the engine stops setting the STF bit As soon as the engine stops the channel registers become inaccessible issuing...

Page 973: ...ncy for PWM Worst case latency for a channel depends both on the function running on that channel and on the activity on other channels Since the 32 eTPU channels must all share the same execution uni...

Page 974: ...ber to analyze performance To analyze the performance of a channel running the PWM function for example some information about what happens in each thread is necessary The following example refers to...

Page 975: ...it is necessary to include the execution time of the second thread Thread information for each function is found in the programming notes for individual TPU functions Refer to Freescale Programming No...

Page 976: ...is reset to state 1 and the scheduler idles until a request is received Priority passing is implemented in hardware and does not contribute to worst case latency 24 6 5 3 2 Time slot transition After...

Page 977: ...s In eTPU the Coherent Dual parameter Controller CDC may also access the SPRAM for atomic transfers of two parameters eTPU Microengine may wait on this operation if it is in service time until the tra...

Page 978: ...2 CPCRWait Average System Clocks for Coherent Parameter Transfer using CDC N2 Number of eTPU eTPU semaphore RAM accesses in the longest thread CCRWait Average System Clocks for Microengine Microengine...

Page 979: ...semaphored These figures will be used for estimating Microengine wait time Table 24 120 is an example for old TPU functions in which there are only simple parameter RAM accesses It does not take into...

Page 980: ...cur after each time slot 24 6 5 4 2 First pass analysis worst case latency examples The examples in this section assume the system configuration shown in Table 24 121 PWM 24 4 SPWM Mode 0 Mode1 Mode 2...

Page 981: ...sses 1 0 09 2 CPU clock waits 10 9 CPU clocks rounded up to 11 CPU clocks Channel 2 worst case service time 11 CPU clocks 2 Assume channel 0 has just been serviced and that channels 1 and 2 are contin...

Page 982: ...us example 2 Assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting service Using the H M H L H M H time slot sequence map the channels that are granted for each...

Page 983: ...M H time slot sequence map the channels that are granted for each time slot See Figure 24 71 Figure 24 71 Next Servicing for Channel 2 Channel 0 will be serviced four times and channel 1 twice before...

Page 984: ...a channel is running the DIO function with a match rate of 20 000 TCR1 counts the DIO will request service every 10 ms 20 000 500 ns 10 000 000 ns or 10 ms It is therefore unrealistic to assume that t...

Page 985: ...for the 50 MHz PWM NOTE This example uses square waves for simplicity Notice that to use a PWM waveform in the typical way in which the pulse is modulated the pulse must not be modulated in a way that...

Page 986: ...nd the WCL for channel 0 assume channel 0 has just finished service Map the channels in the H M H L H M H sequence See Figure 24 72 Figure 24 72 Worst case latency for channel 0 first try Conclusion w...

Page 987: ...hannels 2 and 8 is 4 7 ms which is within the 40 and 80 ms WCL requirements Table 24 126 Second Try system configuration Channel Priority Function1 2 1 0 RAM collision rate 2 CPU clock rate 40 MHz or...

Page 988: ...7 1 1 Execution and channel timing Figure 24 75 shows the main timings related to microinstruction execution when channels and timebases run on T2 timing Table 24 127 Second try system with channel 0...

Page 989: ...2 Timing TCR1 2 T2 T4 T2 T4 T2 T4 1 microcycle 1 microcycle 1 microcycle tn 1 tn MRLA B TDLA B CAP1 2 Pin Action due Match uInstr uInstn uInstn 1 uInst Set Pin Pin Action due uInstr Note TCR clock pre...

Page 990: ...ction 24 5 10 2 Development support features for more details T2 and T4 states are defined as microcycle timing states not to be confounded with logic states of one system clock in which the T clocks...

Page 991: ...pulses of another microcycle Figure 24 77 and Figure 24 78 shows the timing of T2 and T4 timing states respectively Figure 24 77 T2 timing Figure 24 78 T4 timing 24 7 1 2 Input Output signal delays T...

Page 992: ...without any synchronous delays Consult the MCU Reference Manual for information on additional delays added at the integration 24 7 2 Initialization code example The code example below initializes ETPU...

Page 993: ...ned int ETPU_C0HSRR_1_OFFSET ETPU_BASE define ETPU_C1CR_1 volatile unsigned int ETPU_C1CR_1_OFFSET ETPU_BASE define ETPU_C1SCR_1 volatile unsigned int ETPU_C1SCR_1_OFFSET ETPU_BASE define ETPU_C1HSRR_...

Page 994: ...ANNEL_PRIORITY_DISABLE 0x00000000 Channel disable define CHANNEL_PRIORITY_LOW 0x10000000 Low priority channel define CHANNEL_PRIORITY_MIDDLE 0x20000000 Middle priority channel define CHANNEL_PRIORITY_...

Page 995: ..._1 ETPU_C1CR_1 CHANNEL_PRIORITY_HIGH Monitor channel host service request register for completion of initialization HSR should be zero in the end of initialization do temp ETPU_C0HSRR_1 while temp 0 d...

Page 996: ...etection of transB event This is not explicit in the table since it is a general behavior for all double transition submodes A sequence of four events two matches and two transitions are necessary to...

Page 997: ...ansB none 2 transB matchB 2 matchB none 2 transA matchA 1 transB matchB 2 transA matchA 1 matchB none 2 transB none 2 transB matchB 2 em_b_st none matchA matchB both transA matches both transB none 2...

Page 998: ...ransB matchB 2 matchB transB 2 matchB transA 2 sm_st2 matchB matchA none both transA none both transB none 2 transA matchA both transB none 2 sm_dt matchB matchA none both transA none 1 transB none 2...

Page 999: ...C code that calculates the MISC signature for a given array of data based on the previous algorithm define SCM_size MAX_SCM_ADDRESS 4 last byte address converted to 32 bit word define POLY 0x80400007...

Page 1000: ...alculated Average MISC period S 4 f 1 L Eqn 24 1 In Equation 24 1 f clock frequency S SCM size in bytes L eTPU load as a percentage of execution clocks over a period of time including TST clocks Furth...

Page 1001: ...d conversion result As this pin is also used by digital logic it has reduced analog to digital conversion accuracy when compared to the AN 0 11 16 39 analog input pins 25 1 1 2 AN13 MA1 SDO These pins...

Page 1002: ...nversions for a wide range of applications The EQADC provides a parallel interface to two on chip analog to digital converters ADCs a single master to single slave serial interface to an off chip exte...

Page 1003: ...h 4 entries except CFIFO0 that can have 8 entries 1 Decimation filters A and B and Reaction module AN8 ANW AN9 ANX TBIAS AN10 ANY AN11 ANZ AN0 DAN0 AN1 DAN0 AN2 DAN1 AN3 DAN1 AN4 DAN2 AN5 DAN2 AN6 DAN...

Page 1004: ...ws for a full duplex synchronous parallel communication between the EQADC and decimation filters A and B and reaction modules Figure 25 1 also depicts data flow through the EQADC Commands are containe...

Page 1005: ...25 VREF and 75 VREF for ADC calibration purposes 40 input channels available to the two on chip ADCs 4 pairs of differential analog input channels Full duplex synchronous serial interface to an extern...

Page 1006: ...er device s internal trigger The CFIFO0 delivers commands to the ADC as before but those commands are not invalidated after they are sent in fact they are invalidated only because the Transfer Next Da...

Page 1007: ...ll only stop after all on chip ADCs cease executing commands When exiting debug mode the EQADC relies on the CFIFO operation modes and on the CFIFO status to determine the next command entry to transf...

Page 1008: ...time the stop mode entry request is detected there are commands in the on chip CBuffers that were already under execution these commands will be completed but the generated results if any will not be...

Page 1009: ...ot start If the stop mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission the EQADC will complete the abort procedure befor...

Page 1010: ...nput Analog AN16 Input Single ended analog input Analog AN17 Input Single ended analog input Analog AN18 Input Single ended analog input Analog AN19 Input Single ended analog input Analog AN20 Input S...

Page 1011: ...g input DAN1 DAN1 DAN1 AN39 Input Single ended analog input Analog MA0 Output External multiplexer control signal 0 Digital MA1 Output External multiplexer control signal 0 Digital MA2 Output External...

Page 1012: ...a single ended analog input to the two on chip ADCs DAN3 is the positive terminal of the differential analog input DAN3 DAN3 DAN3 25 4 2 8 AN7 DAN3 Single ended analog input Differential analog input...

Page 1013: ...15 Single ended analog input AN15 is a single ended analog inputs to the two on chip ADCs 25 4 2 17 AN16 Single ended analog input AN16 is a single ended analog input to the two on chip ADCs 25 4 2 18...

Page 1014: ...a output signal to the external slave device 25 4 2 29 VRH VRL Voltage reference high and voltage reference low VRH and VRL are voltage references for the ADCs VRH is the highest voltage reference whi...

Page 1015: ...cted EQADC_BASE 0x01 0 EQADC CFIFO Push Register 0 EQADC_CFPR0 Write only EQADC_BASE 0x01 4 EQADC CFIFO Push Register 1 EQADC_CFPR1 Write only EQADC_BASE 0x01 8 EQADC CFIFO Push Register 2 EQADC_CFPR2...

Page 1016: ...Status Register 1 EQADC_FISR1 Unrestricted EQADC_BASE 0x07 8 EQADC FIFO and Interrupt Status Register 2 EQADC_FISR2 Unrestricted EQADC_BASE 0x07 C EQADC FIFO and Interrupt Status Register 3 EQADC_FISR...

Page 1017: ...ister EQADC_REDLCCR Unrestricted EQADC_BASE 0x0D 4 EQADC_BASE 0x0F C Reserved EQADC_BASE 0x10 0 EQADC_BASE 0x10 C EQADC CFIFO0 Registers EQADC_CF0Rw w 0 3 Read only EQADC_BASE 0x11 0 EQADC_BASE 0x11 C...

Page 1018: ...ly EQADC_BASE 0x25 0 EQADC_BASE 0x2F C Reserved EQADC_BASE 0x30 0 EQADC_BASE 0x30 C EQADC RFIFO0 Registers EQADC_RF0Rw w 0 3 Read only EQADC_BASE 0x31 0 EQADC_BASE 0x33 C Reserved EQADC_BASE 0x34 0 EQ...

Page 1019: ...x3D 0 EQADC_BASE 0x3F C Reserved EQADC_BASE 0x40 0 EQADC_BASE 0x40 C EQADC RFIFO4 Registers EQADC_RF4Rw w 0 3 Read only EQADC_BASE 0x41 0 EQADC_BASE 0x43 C Reserved EQADC_BASE 0x44 0 EQADC_BASE 0x44 C...

Page 1020: ...and Enable ADCn n 0 1 ICEAn enables the EQADC to abort on chip ADCn current conversion and to start the immediate conversion command from CFIFO0 in the requested ADCn 1 Enable immediate conversion com...

Page 1021: ...age send format register EQADC_NMSFR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0...

Page 1022: ...FIFO triggers inputs to be recognized as an edge or level gated trigger The Digital Filter Length field specifies the minimum number of system clocks that must be counted by the digital filter counter...

Page 1023: ...nter to recognize a logic state change The count specifies the sample period of the digital filter which is calculated according to the following equation Minimum clock counts for which an ETRIG signa...

Page 1024: ...1 66 0b1001 513 4275 00 0b1010 1025 8541 66 0b1011 2049 17075 00 0b1100 4097 34141 00 0b1101 8193 68275 00 0b1110 16385 136541 66 0b1111 32769 273075 00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0...

Page 1025: ...FO and Interrupt Status Registers EQADC_FISR When the CFIFOx is full the EQADC ignores any write to the CF_PUSHx Reading the EQADC_CFPRx always returns zero Note Only whole words must be written to EQ...

Page 1026: ...RF_POPx contains the next unread entry value of RFIFOx Reading a word a half word or any bytes from EQADC_RFPRx will pop one entry from RFIFOx and cause the RFCTRx field to be decremented by one in th...

Page 1027: ...0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 MODE3 0 0 0 0 W SSE 3 CFIN V3 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Register addres...

Page 1028: ...terrupt Status Registers EQADC_FISR Writing a 1 to SSEx will set the SSSx in Section 25 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR if the CFIFO is in single scan mode When SSSx is alre...

Page 1029: ...be changed to any other mode Note For the streaming mode of operation when the ATRIG0 is used to enable the ETRIG0 or to advance the command queue the normal mode of operation is external trigger sin...

Page 1030: ...igger Operation Mode Table AMODE0 0 3 CFIFO0 Advance Trigger Operation Mode 0b0000 Disabled 0b0001 Reserved 0b0010 Reserved 0b0011 Reserved 0b0100 Falling Edge External Trigger Single Scan 0b0101 Risi...

Page 1031: ...17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R NCIE 3 TORI E3 PIE3 EOQ IE3 CFUI E3 0 CFF E3 CFF S3 0 0 0 0 RFOI E3 0 RFD E3 RFD S3 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Re...

Page 1032: ...ails 1 Enable trigger overrun interrupt request 0 Disable trigger overrun interrupt request PIEx Pause Interrupt Enable x PIEx enables the EQADC to generate an interrupt request when the corresponding...

Page 1033: ...es a combined interrupt at which the Result FIFO Overflow Interrupt the Command FIFO Underflow Interrupt and the Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed When RFOIEx CFUI...

Page 1034: ...te the status of the FIFO itself Figure 25 14 EQADC FIFO and Interrupt Status Register x EQADC_FISRx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NCF x TOR Fx PFx EOQ Fx CFU Fx SSSx CFF Fx 0 0 0 0 0 RFO Fx...

Page 1035: ...pecified CFIFO in edge or level trigger mode Trigger overrun occurs when an already triggered CFIFO receives an additional trigger When TORIEx in Section 25 5 2 8 EQADC Interrupt and DMA Control Regis...

Page 1036: ...erred from CFIFOx CFIFO in edge trigger mode or CFIFO status did not change from TRIGGERED due to detection of a closed gate CFIFO in level trigger mode Note In edge trigger mode an asserted PFx only...

Page 1037: ...The SSSx bit is set by writing a 1 to the SSEx bit in Section 25 5 2 7 EQADC CFIFO Control Registers EQADC_CFCR The EQADC clears the SSSx bit when a command with an asserted EOQ bit is transferred fro...

Page 1038: ...and RFDFx are both asserted an interrupt or a DMA request will be generated depending on the status of the RFDSx bit When RFDSx is negated interrupt requests selected software clears RFDFx by writing...

Page 1039: ...s RFCTRx by one Writing any value to RFCTRx itself has no effect 28 31 POPNXTPTRx 0 3 RFIFOx Pop Next Pointer POPNXTPTRx indicates the index of the entry that will be returned when EQADC_RFPRx is read...

Page 1040: ...15 R 0 0 0 0 0 TC_CF2 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 TC_CF3 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Regi...

Page 1041: ...EQADC CFIFO Transfer Counter Register x EQADC_CFTCRx field description Field Description TC_CFx 0 10 Transfer Counter for CFIFOx TC_CFx counts the number of commands which have been completely transfe...

Page 1042: ...FS5_TCB 1 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 LCFTCB1 TC_LCFTCB1 W RESET 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Regis...

Page 1043: ...py of the corresponding CFSx in the Section 25 5 2 12 EQADC CFIFO Status Register EQADC_CFSR capture at the time a current serial transmission through the EQADC SSI is initiated ECBNI External CBuffer...

Page 1044: ...1 0b0010 Last command was transferred from CFIFO2 0b0011 Last command was transferred from CFIFO3 0b0100 Last command was transferred from CFIFO4 0b0101 Last command was transferred from CFIFO5 0b0110...

Page 1045: ...CQueue in single scan mode Reserved 0b01 Not applicable WAITING FOR TRIGGER 0b10 CFIFO Mode is modified to continuous scan edge or level trigger mode CFIFO Mode is modified to single scan edge or leve...

Page 1046: ...transmissions from the EQADC SSI are disabled See ESSIE field in Section 25 5 2 1 EQADC Module Configuration Register EQADC_MCR 28 31 BR 0 3 Baud Rate Field The BR field selects system clock divide f...

Page 1047: ...b1000 10 0b1001 11 0b1010 12 0b1011 13 0b1100 14 0b1101 15 0b1110 16 0b1111 17 1 If the system clock is divided by a odd number then the serial clock will have a duty cycle different from 50 0 1 2 3 4...

Page 1048: ...result message that was shifted in Writes to the R_DATA have no effect Messages that were not completely received due to a transmission abort will not be copied into EQADC_SSIRDR 0 1 2 3 4 5 6 7 8 9 1...

Page 1049: ...bit entries Refer to Section 25 6 4 EQADC Command FIFOs for more information on CFIFOs These registers are read only Data written to these registers is ignored Table 25 27 STAC Bus Timebase Bits Sele...

Page 1050: ...23 24 25 26 27 28 29 30 31 R CFIFO0_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x100 Register address EQADC_BASE 0x104 Register address EQADC_BASE 0x108 Register address...

Page 1051: ...23 24 25 26 27 28 29 30 31 R CFIFO2_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x180 Register address EQADC_BASE 0x184 Register address EQADC_BASE 0x188 Register address...

Page 1052: ...23 24 25 26 27 28 29 30 31 R CFIFO4_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x200 Register address EQADC_BASE 0x204 Register address EQADC_BASE 0x208 Register address...

Page 1053: ...iption Field Description 0 31 CFIFOx_DATAw 0 31 CFIFOx Data w w 0 3 Reading CFIFOx_DATAw returns the value stored on the wth entry of CFIFOx Each CFIFO is composed of four 32 bit entries with register...

Page 1054: ...r 16 bit entries Refer to Section 25 6 5 EQADC Result FIFOs for more information on RFIFOs These registers are read only Data written to these registers is ignored Figure 25 32 EQADC RFIFO0 Registers...

Page 1055: ...23 24 25 26 27 28 29 30 31 R RFIFO1_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x340 Register address EQADC_BASE 0x344 Register address EQADC_BASE 0x348 Register address...

Page 1056: ...23 24 25 26 27 28 29 30 31 R RFIFO3_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x3C0 Register address EQADC_BASE 0x3C4 Register address EQADC_BASE 0x3C8 Register address...

Page 1057: ...lf word addresses Further the following restrictions apply when accessing these registers Registers ADC0_CR ADC0_GCCR ADC0_OCCR ADC0_AGR1 2 and ADC0_AOR1 2 can only be accessed by configuration comman...

Page 1058: ...d for Alternate Configuration 2 See Section Conversion Command Format for Alternate Configurations Write 0x0A ADC0 ADC1 Conversion Command for Alternate Configuration 3 See Section Conversion Command...

Page 1059: ...guration 6 Control Register ADC_ACR6 Write Read 0x45 Reserved 0x46 Reserved 0x47 Reserved 0x48 Alternate Configuration 7 Control Register ADC_ACR7 Write Read 0x49 Reserved 0x4A Reserved 0x4B Reserved...

Page 1060: ...ted to negated the ADC Clock will not stop until it reaches its low phase 4 ADC0 1_EMUX External Multiplexer enable for ADC0 1 When ADC0 1_EMUX is asserted the MA pins will output digital values accor...

Page 1061: ...signal or the prescaler output signal The prescaler provides the system clock signal divided by a even factor from 2 to 64 This is required to permit the ADC to run as fast as possible when the devic...

Page 1062: ..._ PS 0 ADC0 1_ODD_ PS 1 0b00000 2 3 0b00001 4 5 0b00010 6 7 0b00011 8 9 0b00100 10 11 0b00101 12 13 0b00110 14 15 0b00111 16 17 0b01000 18 19 0b01001 20 21 0b01010 22 23 0b01011 24 25 0b01100 26 27 0b...

Page 1063: ...0b11110 62 63 0b11111 64 65 ADC0 1 Register address 0x02 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 TBC_CLK_PS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Fi...

Page 1064: ...to CBuffer1 A data write to ADC_TBCR through a configuration command sent to CBuffer0 will write the same memory location as when writing to it through a configuration command sent to CBuffer1 NOTE S...

Page 1065: ...returns the current value of time base counter Writes to TBC_VALUE register load the written data to the counter The time base counter counts from 0x0000 to 0xFFFF and wraps when reaching 0xFFFF ADC0...

Page 1066: ...uses one of the alternate configurations when the conversion command with the alternate configuration format is written to an address in the range 0x08 0x0F of the on chip ADC memory map Refer to Sec...

Page 1067: ...he EQADC block but the conversion samples are used by the filter algorithm This feature allows a proper initialization of the Decimation Filter without generating any decimated result Or this bit is u...

Page 1068: ...ace of Decimation filter A The data format is specified by the FMTA bit in the Alternate Configuration Control Register 0010 The conversion result is sent to the Parallel Side Interface of Decimation...

Page 1069: ...Register address 0x31 ADC0 Register address 0x35 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 ALTGCC0x W RESET 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC1 Register address 0x31 ADC1 Register address 0x35 0 1 2...

Page 1070: ...ADC0 Register address 0x36 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 ALTOCC0x W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC1 Register address 0x32 ADC1 Register address 0x36 0 1 2 3 4 5 6 7 8 9 10 11...

Page 1071: ...x ADC_PUDCRx x 0 7 field description Field Description 2 3 CH_PULLx 0 1 Channel x Pull Up Down Control bits The CH_PULLx 0 1 field controls the pull up down configuration of the channel x according t...

Page 1072: ...ecuted again as soon as the critical timing commands have been finished The multiple Result FIFOs RFIFOs can receive data from the on chip ADCs from an off chip external device or from an on chip comp...

Page 1073: ...n streaming mode for popping The FIFO Control Unit expects all incoming results to be shaped in a predefined Result Message format Figure 25 49 shows how result data flows inside the EQADC system Resu...

Page 1074: ...the RFIFO and generating requests to empty it The process of pushing and popping ADC results to and from an RFIFO can occur simultaneously Figure 25 49 Result Flow during EQADC operation 25 6 2 2 Assu...

Page 1075: ...oes not limit the number of RBuffers in the slave device 25 6 2 2 3 Command Execution and Result Return Commands sent to an specific CBuffer should be executed in that order they were received Results...

Page 1076: ...E Although this subsection describes how the command and result messages are formatted to communicate with the on chip ADCs nothing prevents the programmer from using a different format when communica...

Page 1077: ...FO operation mode is configured to single or continuous scan edge trigger mode 1 Enter WAITING FOR TRIGGER state after transfer of the current Command Message 0 Do not enter WAITING FOR TRIGGER state...

Page 1078: ...Data Format FMT specifies to the EQADC how to format the 12 bit conversion data returned by the ADCs into the 16 bit format which is sent to the RFIFOs See Section ADC Result Format for On Chip ADC Op...

Page 1079: ...RFIFOs or to the parallel side interface to communicate with an on chip companion module A bit field in the corresponding Alternate Configuration Control Register selects the Internal RFIFO or Paralle...

Page 1080: ...0b000 then the FFMT bit is used to send a flush soft reset signal through the parallel side interface to the companion module addressed by the DEST field In case DEST is not equal to 0b000 the FMTA bi...

Page 1081: ...and Format for On Chip ADC Operation Table 25 55 Write Configuration Command Format for On Chip ADC Operation field description Field Description 0 EOQ End Of Queue Bit 1 PAUSE Pause Bit 2 REP Repeat...

Page 1082: ...MESSAGE_TAG RESERVED CFIFO Header ADC Command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED ADC_REG_ADDRESS ADC Command Figure 25 53 Read Configuration Command Format for On Chip ADC Opera...

Page 1083: ...or ALTGCC and ALTOCC refer to Section 25 6 6 7 ADC Calibration Feature for details Then this 14 bit data is further formatted into a 16 bit format according to the status of the FMT bit in conversion...

Page 1084: ...command was initiated The two s complement representation is used to express negative values Table 25 58 Correspondence between analog voltages and digital values1 2 VoltageLevel on Channel V Correspo...

Page 1085: ...mand should be sent The remaining 25 bits can be anything decodable by the external device Only the ADC Command portion of a command message is transferred to the external device Differential Conversi...

Page 1086: ...ternal Device Operation field description Field Description 0 EOQ End Of Queue Bit 1 PAUSE Pause Bit Refer to Section Conversion Command Format for the Standard Configuration 4 ABORT_ST ABORT Serial T...

Page 1087: ...to allow visibility of the status of the external CBuffers for debug they could indicate the number of entries in a external CBuffer for example Note After reset the EQADC always assumes that the exte...

Page 1088: ...e null message send format When the EQADC transfers a null message it directly shifts out the 26 bit data content inside the Section 25 5 2 3 EQADC null message send format register EQADC_NMSFR The re...

Page 1089: ...Basic Functionality There are six prioritized CFIFOs located in the EQADC Each CFIFO is four entries deep except CFIFO0 that can be configured to eight entries deep in extended mode and each CFIFO en...

Page 1090: ...e whole 32 bit CF_PUSH field into the corresponding CFIFO but undefined data will fill the areas of CF_PUSH that were not specifically designated as target locations for writing Figure 25 60 describes...

Page 1091: ...full when the Transfer Next Data Pointer x equals the Push Next Data Pointer x and CFCTRx is not zero When the EQADC completes the transfer of an entry from CFIFOx the transferred entry is popped from...

Page 1092: ...hardware implementation has only four entries In this example CFIFOx with 16 entries is shown in sequence after pushing and transferring entries 32 bit Entry 1 32 bit Entry 2 Push Next Data Pointer Tr...

Page 1093: ...t REP bit Push Transfer CFIFOx First In After reset or invalidation Next Data Pointer Next Data Pointer Last In Valid Entry Empty Entry Push Transfer CFIFOx Some entries pushed but none Executed Next...

Page 1094: ...se bit is completed then the queue stops and enters the Pause state waiting for a trigger This is the same as normal behavior The Pause state is exited in one of two ways Repeat Trigger or Repeat Trig...

Page 1095: ...O0 is not starting a new loop In this case outside a loop if a PAUSE bit is decoded this means to disable the Repeat trigger detector This can be useful if the Repeat trigger is not required for some...

Page 1096: ...3 where a CFIFO with 16 entries is shown for clarity of explanation the actual hardware implementation has only four eight entries In this example CFIFO0 with 16 entries is shown in sequence after pus...

Page 1097: ...Pointer Transitory state Repeat trigger with no Entries pushed but not Repeat Pause Repeat Pointer Repeat Pause up to pause bit waiting for trigger Repeat Pause Repeat Pointer Transfer CFIFO0 Next Da...

Page 1098: ...of Queue bit EOQ continues to operate as in normal mode unless the Repeat mode is enabled In this case the Pause bit takes precedence and a Repeat trigger causes the jump back described A Repeat trigg...

Page 1099: ...a command by decoding the EB and BN bits in the command message see Section 25 6 2 3 Message Format in EQADC for details NOTE Triggered but empty CFIFOs underflowing CFIFOs are not considered for pri...

Page 1100: ...ORT_ST bit of the command to be transmitted is asserted the 26th bit of currently transmitting null message has not being shifted out The command from the CFIFO is then written into EQADC SSI transmit...

Page 1101: ...t its transmission However if the previously scheduled data was a command no rescheduling occurs and the next transmission starts without delays If a CFIFO becomes TRIGGERED while SDS is negated but t...

Page 1102: ...the minimum number of system clocks that the ETRIG0 5 signals must be held at a logic level to be recognized as valid All ETRIG signals are filtered A counter for each queue trigger is implemented to...

Page 1103: ...ect new trigger events after an asserted EOQ is detected In continuous scan mode the whole CQueue is scanned multiple times The EQADC also supports different triggering mechanisms for each scan mode T...

Page 1104: ...us to IDLE If the EQADC cannot abort the transfer that is when the 26th bit of the serial message has being already shifted out the EQADC will complete the transfer update TC_CF and then switch CFIFO...

Page 1105: ...bit is encountered the EQADC will clear the SSS bit Setting the SSS bit is required for the EQADC to start the next scan of the queue The Pause bit has no effect in single scan software trigger mode...

Page 1106: ...as no effect in single scan level trigger mode 25 6 4 6 3 Continuous Scan Mode In continuous scan mode multiple passes looping through a sequence of command messages in a CQueue are executed When a CF...

Page 1107: ...CFIFO status until the transmission completes Once the transmission is completed the TC_CF counter is updated the PF flag is asserted and the CFIFO status is changed to WAITING FOR TRIGGER Command tra...

Page 1108: ...Yes None Continuous Scan Level No Gate is opened No No EQADC also stops transfers from the CFIFO when CFIFO status changes from TRIGGERED due to the detection of a closed gate 5 1 Refer to Section 25...

Page 1109: ...ITING FOR TRIGGER 0b10 CFIFO Mode is programmed to continuous scan edge or level trigger mode OR CFIFO Mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO Mode is...

Page 1110: ...s the EOQ bit asserted at end of command transfer and CFIFO Mode is not modified to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from...

Page 1111: ...D due to detection of a closed gate The pause flag interrupt routine can be used to verify if the a complete scan of the CQueue was performed If a closed gate is detected while no command transfers ar...

Page 1112: ...uence is coherent if while it is transferring commands to a CBuffer the buffer is only fed with commands from that sequence without ever becoming empty A command sequence starts when a CFIFO in TRIGGE...

Page 1113: ...F5_CB1_CM3 CF5_CB0_CM4 CF5_CB2_CM5 CF5_CB1_CM6 EOQ 1 command sequences Example 3 Example 1 Example 2 CQueue with a two command sequences Assuming that these commands are transferred by a CFIFO configu...

Page 1114: ...the last result message received from external device is encoded as Send available commands CBuffer is empty Refer to Section Result Message Format for External Device Operation The NCF flag becomes a...

Page 1115: ...igure 25 73 depicts how the non coherency hardware will behave when a non coherency event is detected NOTE If MODEx is changed to disabled while a CFIFO is transferring commands the NCF flag for that...

Page 1116: ...1 CF5_CB1_CM2 2 CF5_CB1_CM3 3 CF0_CB1_CM0 0 CF0_CB1_CM1 1 CF0_CB1_CM2 2 CF0_CB1_CM3 3 TNXTPTR CF5_CB1_CM0 0 CF5_CB1_CM1 1 CBuffer1 CFIFO5 CFIFO0 TNXTPTR Sent 0 Sent 1 CF5_CB1_CM2 2 CF5_CB1_CM3 3 Sent...

Page 1117: ...fer3 EQADC SSI b CFIFO0 is triggered and sent two commands to CBuffer2 CFIFO5 cannot send commands to CBuffer3 because the EQADC SSI is busy transferring commands from CFIFO0 Execution of first comman...

Page 1118: ...ese requests by reading Section 25 5 2 6 EQADC Result FIFO Pop Registers EQADC_RFPR to retrieve data from the RFIFO NOTE The DMAC should be configured to read a single result 16 bit data from the RFIF...

Page 1119: ...contained in a RFIFO four in this implementation When a new message arrives and RFIFOx is not full the EQADC copies its contents into the entry pointed by the Receive Next Data Pointer The RFIFO count...

Page 1120: ...mplementation has only four entries In this example RFIFOx with 16 entries is shown in sequence after popping or receiving entries Data Entry 2 Data Entry 1 POP Next Data Pointer Receive Next Data Poi...

Page 1121: ...received but none popped Next Data Pointer Next Data Pointer Pop RFIFOx No entries received but some popped Next Data Pointer First In Last In Receive Next Data Pointer Receive RFIFOx Entries receive...

Page 1122: ...ult data from the external device is only processed after all data from ADC0 1 is processed and finally returned data from companion module is only processed after all data from ADC0 1 and external de...

Page 1123: ...0_CR and ADC1_CR When the ADC0 1_CLK_SEL is set the ADC clock frequency is the same as the system clock but it has the inverted phase When it is clear the ADC0 1_ODD_PS and the ADC0 1_CLK_PS fields se...

Page 1124: ...to the system clock frequency certain clock divide factors are invalid 2 4 6 8 clock divide factors in the example since their use would result in a ADC clock frequency higher than the maximum one sup...

Page 1125: ...sps 188 Ksps 1 41 2 93 MHz 195 Ksps 183 Ksps 0b10100 0 42 2 86 MHz 190 Ksps 179 Ksps 1 43 2 79 MHz 186 Ksps 174 Ksps 0b10101 0 44 2 73 MHz 182 Ksps 170 Ksps 1 45 2 67 MHz 178 Ksps 167 Ksps 0b10110 0 4...

Page 1126: ...specified in the MESSAGE_TAG field of the executed conversion command The time stamp can be provided by an external source using the STAC bus interface more details in Section 25 6 6 4 1 STAC Client S...

Page 1127: ...ases running at system clock divided by four or slower can be integrally exported The STAC client submodule runs with the system clock and its time slot timing is synchronized with the eTPU2 timing on...

Page 1128: ...3 6 Alternate Configuration 1 8 Control Registers ADC_ACR1 8 For conversions at a resolution less than 12 the ADC is executing less operations and the conversion time is smaller In this ADC it is ver...

Page 1129: ...re is a Multiply and Accumulate MAC unit one per on chip ADC that is used to calculate the following transfer function which relates a calibrated result to a raw uncalibrated one CAL_RES GCC RAW_RES O...

Page 1130: ...it is the direct output from the on chip ADCs but passing through the resolution adjustment block The GCC0 1 operand is a 15 bit fixed point unsigned value stored in the Section 25 5 3 4 ADC0 1 Gain C...

Page 1131: ...rsion results from right aligned format of ADC to the left aligned format depending on the selected resolution of the conversion This operation helps the calibration processing to use the calibration...

Page 1132: ...then the channel number of ENTRY0 is sent to the MUX Control Logic some cycles before the sampling phase of the command in ENTRY0 starts In this way sampling for the next command can promptly start af...

Page 1133: ...GE_TAG1 FMT1 CAL1 EMUX1 TBC_CLK_PS 32 bits MA0 MA1 MA2 ENTRY1 ENTRY0 Configuration ENTRY1 ENTRY0 TSR1 ADDR or and DATA ADDR or and DATA Register Data 0 1 CHANNEL_NUMBER0 Time Stamp1 Registers CBuffer1...

Page 1134: ...ifferential signals to both the positive and negative terminals of the ADC The differential conversions can only be initiated on four channels DAN0 Channel Change and Sample Start a Command Execution...

Page 1135: ...hannel Number in CHANNEL_NUMBER Field Analog Pin Name Other Functions Conversion Type ADC Number Binary Decimal AN0 to AN39 Single ended ADC0 ADC1 0000_0000 to 0010_0111 0 to 39 VRH Single ended ADC0...

Page 1136: ...9 INA_ADC1_3 Device Specific Single ended ADC1 1100_0010 194 INA_ADC1_4 Device Specific Single ended ADC1 1100_0011 195 INA_ADC1_5 Device Specific Single ended ADC1 1100_0100 196 INA_ADC1_6 Device Spe...

Page 1137: ..._1110 to 0011_1111 46 to 63 ANW Single ended ADC0 ADC1 0100_0xxx 64 to 71 ANX Single ended ADC0 ADC1 0100_1xxx 72 to 79 ANY Single ended ADC0 ADC1 0101_0xxx 80 to 87 ANZ Single ended ADC0 ADC1 0101_1x...

Page 1138: ...1100_0001 168 to 193 Reserved ADC0 1100_0010 to 1100_0111 194 to 199 INA_ADC1_3 Device Specific Single ended ADC1 1100_0010 194 INA_ADC1_4 Device Specific Single ended ADC1 1100_0011 195 INA_ADC1_5 De...

Page 1139: ...ANY and ANZ The MA pins correspond to the three least significant bits of the channel number that selects ANR ANS ANT ANU ANW ANX ANY and ANZ with MA0 being the most significant bit See Table 25 71 Wh...

Page 1140: ...AN84 AN85 AN86 AN87 MUX AN88 AN89 AN90 AN91 AN92 AN93 AN94 AN95 ANW ANX ANY ANZ 4 AN0 AN7 32 40 MUX 40 1 MUX 40 1 ADC0 ADC1 MUX CONTROL Channel Number0 1 EQADC AN12 AN15 NOTE Limited availability of...

Page 1141: ...CFIFO Underflow Interrupt and a CFIFO Trigger Overrun Interrupt occurs the EQADC also provides a combined interrupt request at which these requests from ALL CFIFOs are ORed Refer to Figure 25 84 for d...

Page 1142: ...OQIEx EOQFx CFUIEx CFUFx RFOIEx RFOFx Non Coherency Interrupt Request Pause Interrupt Request End of Queue Interrupt Request Trigger Overrun Interrupt Request CFIFO Underflow Interrupt Request RFIFO O...

Page 1143: ...o indicate the end or the abort of a transmission SDI is the master serial data input and SDO the master serial data output The EQADC SSI sub block is enabled by setting the ESSIE field in the Section...

Page 1144: ...EQADC SSI data transmission protocol Figure 25 87 shows the timing of an EQADC SSI transmission operation The main characteristics of this protocol are FCK is free running it does not stop between da...

Page 1145: ...is not used as a clock Although the EQADC SSI behavior is described in terms of the FCK positive and negative edges all EQADC SSI related signals SDI SDS SDO and FCK are synchronized by the system clo...

Page 1146: ...Interface Protocol Timing 2 3 23 24 25 26 2 3 23 24 25 2 3 23 24 25 2 3 23 24 25 FCK SDS SDO Master Sample SDI Slave Sample Input Input tDT Begin Transmission Begin Transmission End Transmission End T...

Page 1147: ...ive edge of FCK Master s SDI 25 26 1 2 3 25 26 1 2 3 25 26 1 1 2 3 SDS FCK Slave Sample Input tDT tDT tDT Begin Transmission Begin Transmission Begin Transmission End Transmission End Transmission SDS...

Page 1148: ...version result data When the DEST field is not zero as described in Section 25 5 3 6 Alternate Configuration 1 8 Control Registers ADC_ACR1 8 the MESSAGE_TAG bits and some control bits and the convers...

Page 1149: ...r the control of the companion module MESSAGE_TAG 0 3 Message tag bits field Read Input Write Output Data Buses Content 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 TAG 0 3 W FLU SH CTRL 0 1 MESSAG...

Page 1150: ...ter Write section The transmission sub block formats the data bus from RFIFO control sub block to send to the PSI slave wdata bus The transmission data is registered and its content is described in Se...

Page 1151: ...RSD stage and then from the RSD stage output back to its input to be passed again To complete a 12 bit conversion the signal must pass through the RSD stage 12 times For 10 bit and 8 bit resolution t...

Page 1152: ...g on the two comparator inputs As the Logic Control sets the summing operation it also sends a digital value to the RSD adder Each time an analog signal passes through the RSD single stage a digital v...

Page 1153: ...nput phase and after each of the 12 passes through the RSD stage Thus 13 total a and b values are collected Upon collecting all these values they will be added according to the RSD algorithm to create...

Page 1154: ...imes before the normal conversion processing 25 7 Initialization Application information 25 7 1 Multiple queues control setup example This section provides an example of how to configure multiple CQue...

Page 1155: ...der to avoid unexpected triggering of CFIFOs in hardware trigger modes the source driving the ETRIG port must be selected and set to a known logic level before putting the CFIFOs into the WAITING FOR...

Page 1156: ...9 EQADC FIFO and Interrupt Status Registers EQADC_FISR will be set The EQADC generates a End of Queue interrupt The initialization procedure is complete Figure 25 95 Example of a CQueue Configuring th...

Page 1157: ...quested the result See Section 25 6 2 3 Message Format in EQADC for details Step One Setup the CQueues and RQueues 1 Load the RAM with configuration and conversion commands Table 25 76 is an example o...

Page 1158: ...FDE3 and CFFE1 to enable the EQADC to generate DMA requests Command transfers from the RAM to the CFIFO1 will start immediately e Set RFOIE3 to indicate if RFIFO3 overflows f Set CFUIE1 to indicate if...

Page 1159: ...For every DMA request issued by the EQADC the DMAC has to be configured to transfer a single command 32 bit data from the CQueue pointed to by the source address to the CFIFO push register pointed to...

Page 1160: ...A channel should be disabled The destination address should be updated pointed to the next location where new coming results are stored which can be the first entry of the current RQueue cyclic queue...

Page 1161: ...details on disabling a CFIFO are described in Section 25 6 4 6 1 Disabled Mode 1 Determine the resumption conditions when later resuming the scan of the CQueue at the point before it was modified a C...

Page 1162: ...ll be stored in RQueue0 and RQueue1 and CQueue1 commands requesting results that will be stored only in RQueue1 Some Command Messages request data to be returned from the on chip ADC external device b...

Page 1163: ...to RQueue1 CQueue1 Read Command 1 0x0004 Result to RQueue1 CQueue1 Conversion Command 2 0x0008 Result to RQueue1 CQueue1 Conversion Command m 0x001C Command Queue 1 CQueue1 Result CQueue1 Read Comman...

Page 1164: ...ed results for these input voltages are obtained by converting these channels with conversion commands that have the CAL bit negated The transfer equations for when sampling these reference voltages a...

Page 1165: ...ue and OCC is a signed 14 bit value 5 Write GCC value to Section 25 5 3 4 ADC0 1 Gain Calibration Constant Registers ADC0_GCCR and ADC1_GCCR and OCC value to Section 25 5 3 5 ADC0 1 Offset Calibration...

Page 1166: ...ced by half leading to an increase in accuracy Figure 25 99 Quantization error reduction during calibration 25 7 7 EQADC versus QADC This section describes how the EQADC upgrades the QADC functionalit...

Page 1167: ...1167 familiar with terminology in QADC Figure 25 100 is an overview of a QADC Figure 25 101 is an overview of the EQADC system Figure 25 100 QADC Overview External Triggers Result Queues Command Queu...

Page 1168: ...EQADC SSI is implemented to transmit and receive data between the EQADC and the external device Since there are only FIFOs inside the EQADC much of the terminology or use of the register names registe...

Page 1169: ...e QADC detecting a pause bit in the CCW will pause the queue execution In the EQADC detecting a pause bit in the Command will pause command transfers from a CFIFO Queue Operation Mode MQx CFIFO Operat...

Page 1170: ...6 1170 Freescale Semiconductor Queue Execution Require Software or External Trigger events to start queue execution Require Software or External Trigger events to start command transfers from a CFIFO...

Page 1171: ...urations with address from 1 to 6 can be sent to the internal RFIFO or to the eQADC dedicated slave bus interface to communicate with the external Decimation Filter IP block or any other block that ca...

Page 1172: ...o work in a standalone mode In this mode the input data is supplied and the output results are read by the chip core processor CPU using status and interrupt signals or DMA requests Mixed modes are al...

Page 1173: ...with 51 bit fixed point accumulator Convergent rounding methodology Two s complement overflow or saturation selection 58 clock cycles to process the input Implements a local slave bus interface to a m...

Page 1174: ...he decimation filter block It corresponds to the prefill filter operation with input data supplied through the PSI slave bus interface i e its input data is the ADC conversion result with output going...

Page 1175: ...t of the next block middle or tail block to be filtered again More details in Section 26 5 16 Cascade mode description 26 2 3 6 Low Power mode Low power mode corresponds to the module disable mode or...

Page 1176: ...the device integration and the second is related to a PSI master block for data transfers Below both memory maps are described 26 4 1 Decimation filter device memory map The addresses of the Decimatio...

Page 1177: ...d 0x078 Decimation Filter TAP0 Register DECFILTER_TAP0 1 on page 26 1195 0x07C Decimation Filter TAP1 Register DECFILTER_TAP1 0x080 Decimation Filter TAP2 Register DECFILTER_TAP2 0x084 Decimation Filt...

Page 1178: ...page 26 1198 0x0EC Decimation Filter Current Integration Count Value Register DECFILTER_CINTCNT on page 26 1199 0x0F0 0x1FF Reserved 1 The TAP register stores on each filter node the input sample dat...

Page 1179: ...de the MAC operations are halted See Section 26 5 13 Freeze mode description for more details 1 Decimation Filter in Freeze Mode 0 Decimation Filter in Normal Mode 4 SRES Software reset bit The SRES i...

Page 1180: ...0 Reserved should be cleared FTYPE 1 0 11 12 Filter Type Selection bits The FTYPE 1 0 bits select the filter type according to Table 26 6 Note Bypass must not be configured in cascade mode see field C...

Page 1181: ...s interface or the CPU DMA on the device slave bus interface Each device slave bus write to the Interface Input Buffer register or DMA transfer to the input buffer is interpreted as a new sample to be...

Page 1182: ...8 ISEL MIXM definition Read Write from to Input Output buffers ISEL MIXM Mode Operation Device slave bus Interface PSI slave bus interface Input Buffer Output Buffer Input Buffer Output Buffer 0 0 No...

Page 1183: ...the Decimation Filter to generate interrupt requests when device slave bus input is selected ISEL 1 and DSEL 0 when the input buffer is available to receive new data PSI input is selected with Enhanc...

Page 1184: ...g function enabled by the TORE bit as shown in Table 26 10 Note The TMODE definition replaces and is upward compatible with the TRFE bit definition found in previous versions of the Decimation Filter...

Page 1185: ...tus Register This bit is self negated therefore it is always read as zero 1 Clears IDF 0 No action 7 ODFC Output Data Flag Clear bit The ODFC bit clears the ODF Flag bit in the Status Register This bi...

Page 1186: ...e input buffer DECFILTER_IB is available to be filled with new data when Enhanced Debug Monitor is off In Enhanced Debug Monitor it indicates the input buffer DECFILTER_IB was filled with a new sample...

Page 1187: ...put Overrun 31 IVR Input Interface Buffer Overrun The IVR bit indicates that a received sample in the Filter Interface Input Register was overwritten by a new sample This was probably caused by a viol...

Page 1188: ...led integration therefore one must not configure SSIG 1 and SSAT 0 3 SCSAT Integrator Counter Saturated operation selection The SCSAT bit defines how the integrator sample counter behaves in case of a...

Page 1189: ...ts independently of the enabling selected by SENSEL For more details see Section 26 5 15 4 Integrator enabling and halting 24 Reserved should be cleared Table 26 12 DECFILTER_MXCR Register Field Descr...

Page 1190: ...selected by the SISEL bit are added to the integration accumulator When the integrator is disabled the integration accumulator remains unaltered on filter outputs For more details see Section 26 5 15...

Page 1191: ...0 0 0 0 0 Figure 26 5 Decimation Filter Extended Status Register DECFILTER_MXSR Table 26 17 DECFILTER_MXSR Register Field Descriptions Field Description 0 6 Reserved should be cleared 7 SDFC Integrat...

Page 1192: ...DECFILTER_MCR bit ERREN and it is cleared by the SSEC bit or by a soft reset Integrator exceptions are defined in Section 26 5 15 5 Integrator exceptions 1 Integrator accumulator exception 0 No except...

Page 1193: ...tegrator Data Overrun The SVR bit indicates that an integration value and count in the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT was overwritten by a new integrator output request and was not...

Page 1194: ...6 5 3 Input buffer description for more details Address DECFILTER_BASE 0x014 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 OUTTAG 3 0 W Reset 0 0 0 0 0 0 0 0 0...

Page 1195: ...tal filter coefficients registers The coefficients are fractional signed values in two s complement format in the range 1 coef 1 Note Reads to this register are sign extended meaning the coefficient s...

Page 1196: ...escription for more details Writes to this register are not allowed Address DECFILTER_BASE 0x0D0 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0...

Page 1197: ...20 21 22 23 24 25 26 27 28 29 30 31 R SUM_VALUE 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 11 Decimation Filter Final Integration Value Register DECFILTER_FINTVAL Table 26 23 DECFILTER_FIN...

Page 1198: ...this register is determined by the register DECFILTER_MXCR see Section 26 4 2 3 Decimation Filter Module Extended Configuration Register DECFILTER_MXCR The register is updated together with DECFILTER_...

Page 1199: ...he output buffers of the filter To implement this exchange only a single register is required as described in Table 26 27 therefore the PSI address is ignored Address DECFILTER_BASE 0x0EC Access User...

Page 1200: ...ddress PSI_BASE 0x0 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 OUT_TAG 3 0 W M_FLUSH M_CTRL 1 0 INP_TAG 3 0 Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 1201: ...ster can be written with this data when ISEL 0 This data can be timestamp information that is not processed by the filter or sample data that is processed by the digital filter In this case the inform...

Page 1202: ...ible for communication and data exchange between the master block for instance the eQADC block and the Decimation Filter block The decimation filter receives sample data from the master block The inpu...

Page 1203: ...write read request that was generated in any mode 26 5 3 1 Input buffer overrun An input overrun occurs when the input buffer is holding input data and new data is received by the filter See Section...

Page 1204: ...request if DSEL 1 in standalone or PSI input mixed modes When the filter is bypassed FTYPE 00 and PSI is selected as output normal mode or PSI output mixed mode the data written into the input buffer...

Page 1205: ...in the configuration register DECFILTER_MCR When triggered output is enabled the decimation count configured by DECFILTER_MCR field DEC_COUNTER is ignored The decimation filter detects the rising edg...

Page 1206: ...s the filter algorithm Figure 26 16 1 x 4 poles IIR filter functional diagram The difference equation for the IIR filter of Figure 26 16 can be written as Eqn 26 1 where x n is the filter input at tim...

Page 1207: ...case the order of the FIR filter is twice the IIR filter order since all the TAP and coefficient registers are allocated for the FIR section The Filter configuration paths are shown in Figure 26 18 M...

Page 1208: ...ber which makes the decision on rounding up or down based on the value of the lower portion of data to be rounded LS_WORD The rounding up down condition is equal to the traditional rounding except whe...

Page 1209: ...ter without generating decimated samples In addition the prefill does not operate when the filter is in bypass FTYPE 0b00 The prefill is controlled by the value in the M_CTRL 1 0 field in the DECFILTE...

Page 1210: ...Similarly when the filter is decimating the results the timestamp is only sent to the output buffer if the corresponding received conversion data has generated a filter output that is selected by the...

Page 1211: ...IDIS 1 2 poll the register DECFIL_MSR until the bit BSY is 0 3 repeat the step 2 polling this is necessary to cover the case when a sample is left in the input buffer 4 write DECFILTER_MCR bit SRES 1...

Page 1212: ...he decimation filter input flagged by IVR Overrun in the decimation filter output flagged by OVR Overrun in enhanced debug monitor flagged by DIVR Integrator overrun flagged by SVR Integrator value ex...

Page 1213: ...fer interrupt request is asserted when the output buffer receives a new result from the filter sub block This means the block is requesting data to be read by the CPU The output buffer interrupt reque...

Page 1214: ...request during the processing of an input sample the current processing is finished and then the module enters freeze mode Access to input and output buffers remain operational in freeze as well as t...

Page 1215: ...ed for signed operation SSIG 1 The fractional part of the accumulation is 15 bits wide in both cases An accumulation overflow is flagged by the DECFILTER_MXSR bit SSOVF The accumulator can overflow in...

Page 1216: ...MA integrator requests The integrator DMA request uses the same signal as the filter output DMA request so one must never use any configuration that allows both the integrator and filter output to mak...

Page 1217: ...and and output request by hardware signal the SSOVF and SCOVF flags do not negate however the internal overflow states which assert SSOVF and SCOVF do reset immediately so that the next output update...

Page 1218: ...TER_CINTVAL is read based on the internal accumulator overflow state Similarly the sample counter exception condition depends on whether it operates in saturated mode or not as follows In Saturated op...

Page 1219: ...cribed in Section 26 5 16 2 Cascade Mode Data Control Bus description The arrows show how they are physically connected The bold arrows show the connections used in cascade mode The block configuratio...

Page 1220: ...L 0 for PSI ISEL 1 for device slave bus DECFILTER_MCR bit MIXM must be written 0 for all cascaded blocks Head PSI master block cascade cascade Optional connections PSI bus Tail PSI bus Middle PSI bus...

Page 1221: ...PSI bus Head PSI bus in out in out in out in out data in data out out in cascade cascade out in cascade cascade out in cascade cascade out in chain in chain in chain in physical connection unused in c...

Page 1222: ...d with its input disabled When the mode configuration is done the combo blocks must have their inputs enabled in order from the Tail towards the Head block A single block must also be reconfigured the...

Page 1223: ...FCIN OUT_REQ Decimation Filter Cascade Request The DFCIN OUT_REQ bit indicates that a cascade bus driver block in a cascade configuration has data ready to be sent The driven block responds to the req...

Page 1224: ...ion is shown in Figure 26 24 In this case the Decimation Filter receives conversion results generated by the eQADC block These results can be generated from eight different ADC setup configurations wh...

Page 1225: ...isy input data The expected output values and the RMS error were then calculated 26 8 1 Coefficients calculation The coefficients were calculated using a digital filter design tool We have supplied so...

Page 1226: ...les in the range 1 sample 1 It is supposed the input data are signed values in the two s complement format in the range 1 sample 1 Table 26 32 Coefficient values given by SPW digital filter design too...

Page 1227: ...nts and the input data samples A scaling factor of eight in the configuration register DECFILTER_MCR and no decimation factor were used to obtain the maximum of output results from the filter The theo...

Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...

Page 1229: ...al to absolute temperature This voltage VTSENS T is read by software using the onboard eQADC module and used with the bandgap voltage and constants stored in flash memory during factory test to calcul...

Page 1230: ...Reference Manual Rev 6 1230 Freescale Semiconductor Figure 27 1 Calibration points 27 3 Temperature formula The temperature formula is shown in Figure 27 2 T JUNCTION VBG TLOW THIGH T JUNCTION VTSENS...

Page 1231: ...are stored in shadow flash memory during factory calibration See Section 27 3 6 1 Temperature Calculation Constants Register 0 TSENS_TCCR0 for details VBG_CODE TLOW TTSENS_CODE T x TTSENS_CODE TLOW TT...

Page 1232: ...he bandgap reference voltage Software must sample the voltage from eQADC_A channel 144 ADC0 27 3 6 Registers The calibration constants described previously that is TLOW THIGH TSENS_CODE TLOW TSENS_COD...

Page 1233: ...mpled and converted by the eQADC during factory test with device at hot temperature THIGH This is the TSENS_CODE THIGH parameter value referenced in the temperature calculation formula see Figure 27 2...

Page 1234: ...ed W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 27 2 Temperature Calculation Constants Register 1 TSENS_TCCR1 field descriptions Field Bits Description Reserved 0 1 Reserved...

Page 1235: ...ocontroller temperature sensor calibration values from address offset 0x00 0x3C NOTE The SIM base address is 0xFFFE_C000 same as the temperature sensor base The temperature sensor calibration values a...

Page 1236: ...System Information Module and Trim SIM MPC5644A Microcontroller Reference Manual Rev 6 1236 Freescale Semiconductor...

Page 1237: ...s of computing CRC checksums but there are many articles to be found via internet searches One that might be of particular interest is A Painless Guide to CRC Error Detection Algorithms by Ross Willia...

Page 1238: ...actually mapped to a register 29 3 Calculating a CRC checksum The MPC5644A CRC module has three independent sets of CRC engines and registers each set called a context Each context supports a single d...

Page 1239: ...o be performed on the output Specifying whether a bit inversion is to be performed on the output Selections are made by writing the appropriate values to fields in the CRC_CFG register Two standard po...

Page 1240: ...checksum calculation is performed i e during the configuration phase the CRC_CSTAT register is used to program the seed value During CRC checksum calculation the register contains the current checksum...

Page 1241: ...utation 29 4 Register descriptions Table 29 1 CRC register map Context Address1 1 CRC_BASE for the MPC5644A is 0xFFE6_8000 Register Location 1 CRC_BASE 0x0000 CRC Configuration Register CRC_CFG on pag...

Page 1242: ...rved 29 POLYG POLYG Polynomial selection 0 CRC CCITT polynomial 1 CRC 32 polynomial This bit can be read and written by software This bit can be written only during the configuration phase 30 SWAP SWA...

Page 1243: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 3 CRC Input Register CRC_INP Table 29 3 CRC_INP field descri...

Page 1244: ...1 1 1 1 1 1 1 Figure 29 4 CRC Current Status Register CRC_CSTAT Table 29 4 CRC_CSTAT field descriptions Field Description 0 31 CSTAT Status of the CRC signature The CSTAT register includes the current...

Page 1245: ...21 22 23 24 25 26 27 28 29 30 31 R OUTP W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 29 5 CRC Output Register CRC_OUTP Table 29 5 CRC_OUTP field descriptions Field Description 0 31 OUTP Final CRC si...

Page 1246: ...f a CRC checksum calculation 29 5 2 Calculations on incoming outgoing protocol frames The following sections show the sequence for managing CRC checksums as part of a communication external to the dev...

Page 1247: ...tor 1247 Figure 29 6 Transmission sequence Data to be Transmitted CRC_OUTP CRC_INP Memory CRC Context CPU Transmission Phase 2 Data to be Transmitted CRC_OUTP CRC_INP Memory CRC Context DMA Transmissi...

Page 1248: ...ata stream The sequence is as follows 1 Software configures the DMA channel and CRC context to be used 2 DMA copies the received data block payload CRC from the peripheral e g SPI Rx FIFO module to me...

Page 1249: ...escale Semiconductor 1249 Figure 29 7 Reception sequence CRC_OUTP CRC_INP Memory CRC Context DMA Received Data CRC Checksum Received Data Rx FIFO Memory SPI DMA Reception Phase 1 CRC Checksum Received...

Page 1250: ...Cyclic Redundancy Checker CRC Unit MPC5644A Microcontroller Reference Manual Rev 6 1250 Freescale Semiconductor...

Page 1251: ...ides a synchronous serial interface for communication between the MPC5644A and external devices The DSPI supports pin count reduction through serialization and deserialization of eTPU channels eMIOS c...

Page 1252: ...f the eDMA controller or through host software 30 3 Features The DSPI supports these SPI features Full duplex synchronous transfers Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins only in...

Page 1253: ...lement a 32 bit Timed Serial Bus TSB configuration supporting the Micro Second Channel MSC bus downstream frame format The DSPIs also support these features unique to the DSI and CSI configurations 2...

Page 1254: ...MA controller or host CPU Figure 30 2 shows a system example with DMA DSPI and external queues in system RAM Figure 30 2 DSPI with queues and DMA 30 4 2 DSI configuration The DSI configuration support...

Page 1255: ...the CSI configuration transmission of SPI data has higher priority than DSI data The data returned from the bus slave is either used to drive the eTPUs or eMIOS input channels or the data is stored i...

Page 1256: ...ly controlled serial transfers The DSPI cannot initiate serial transfers in Slave Mode 30 6 3 Module Disable mode The Module Disable mode is used for MCU power management The clock to the non memory m...

Page 1257: ...RIG Peripheral Chip Select 4 Master Trigger In master mode DSPI_x_PCS 4 is a Peripheral Chip Select output signal In slave mode the active low MTRIG is an output trigger signal that indicates that a c...

Page 1258: ...t signal 30 7 2 7 DSPI_x_SCK Serial clock DSPI_x_SCK is a serial communication clock signal In master mode the DSPI generates the SCK In slave mode SCK is an input from an external bus master 30 7 2 8...

Page 1259: ...1274 DSPI_BASE 0x38 DSPI Pop RX FIFO Register DSPI_POPR on page 30 1276 DSPI_BASE 0x3C DSPI_BASE 0x48 DSPI Transmit FIFO Register 0 DSPI_TXFR0 DSPI Transmit FIFO Register 3 DSPI_TXFR3 on page 30 1277...

Page 1260: ...Register 2 DPSI_PISR2 1 on page 30 1285 DSPI_BASE 0xE4 DSPI DSI Parallel Input Select Register 3 DPSI_PISR3 1 on page 30 1285 DSPI_BASE 0xE8 DSPI DSI Deserialized Data Interrupt Mask Register DSPI_DI...

Page 1261: ...Chip Select Strobe Enable The PCSSE bit enables the DSPI_x_PCS 5 PCSS to operate as a PCS Strobe output signal See Section 30 9 5 5 Peripheral chip select strobe enable PCSS for more information 0 DSP...

Page 1262: ...Writing a 1 to CLR_TXF clears the TX FIFO Counter The CLR_TXF bit is always read as zero 0 Do not clear the TX FIFO Counter 1 Clear the TX FIFO Counter 21 CLR_RXF Clear RX FIFO CLR_RXF is used to flus...

Page 1263: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 6 DSPI Hardware Configuration Register DSPI_HCR Table 30 5 DSPI_HCR field description Field Description DSI DSI feature...

Page 1264: ...DSPI_DSICR selects which of the DSPI_CTAR register is used When the DSPI is configured as a DSI bus slave the DSPI_CTAR1 register is used In CSI Configuration the transfer attributes are selected bas...

Page 1265: ...er transfer can be set from 1 to 64 serial clocks with help of PDT and DT fields Address DSPI_BASE 0xC DSPI_BASE 0x28 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBR FMSZ CPOL CPHA LSBFE PCSSCK PASC PDT P...

Page 1266: ...unication between serial devices the devices must have identical clock polarities When the Continuous selection format is selected switching between clock polarities without stopping the DSPI can caus...

Page 1267: ...e Baud Rate is the frequency of the Serial Communications Clock SCK The system clock is divided by the prescaler value before the baud rate selection takes place See the BR field description for detai...

Page 1268: ...nd DT fields plus 1 of the SCK clock periods See Section 30 9 5 4 Delay after transfer tDT for more details 28 31 BR 0 3 Baud Rate Scaler The BR field selects the scaler value for the baud rate This f...

Page 1269: ...valid FMSZ field value is 3 5 CPOL Clock Polarity The CPOL bit selects the inactive state of the Serial Communications Clock SCK 0 The inactive state value of SCK is low 1 The inactive state value of...

Page 1270: ...ot used write always zero to keep software compatible with future updates Address DSPI_BASE 0x2C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0 DPEF SPEF DDIF RFOF 0 RFDF 0 W...

Page 1271: ...e TX FIFO The TFFF bit is set while the TX FIFO is not full The TFFF bit can be cleared by writing 1 to it or by acknowledgement from the DMA controller to the TX FIFO full request 0 TX FIFO is full 1...

Page 1272: ...y is transmitted during the next transfer The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift register See Section 30 9 10 4 Transmit FIFO underflow interrup...

Page 1273: ...terrupt requests or DMA requests are enabled 7 TFFFDIRS Transmit FIFO Fill DMA or Interrupt Request Select The TFFFDIRS bit selects between generating a DMA request or an interrupt request When the TF...

Page 1274: ...DSPI_SR to generate a request The RFDFDIRS bit selects between generating an interrupt request or a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA...

Page 1275: ...rrent SPI transfer is the last in a queue At the end of the transfer the EOQF bit in the DSPI_SR is set 0 The SPI data is not the last data to transfer 1 The SPI data is the last data to transfer 5 CT...

Page 1276: ...34 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 13...

Page 1277: ...er of registers used to implement the RX FIFO is device specific If a four entry RX FIFO is implemented DSPI_RXFR0 DSPI_RXFR3 exist for example Table 30 16 DSPI_POPR field description Field Descriptio...

Page 1278: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 16 DSPI Receive FIFO Registers 0 15 DSPI_RXFR0 DSPI_RXFR15 Table 30 18 DSPI_RXFRn field descripti...

Page 1279: ...ws tDT to be programmable See Section 30 9 8 Timed serial bus TSB for detailed information 0 Timed Serial Bus Configuration disabled 1 Timed Serial Bus Configuration enabled If this bit is clear the D...

Page 1280: ...sed in DSI master mode In DSI slave mode the DSPI_CTAR1 is always selected 20 DMS Data Match Stop DMS bit if set stops DSI frames transmissions if DDIF flag is set in the DSPI_SR register 0 DDIF flag...

Page 1281: ...11 12 13 14 15 R SER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 18 DSPI DSI Serializatio...

Page 1282: ...ls The DSPI_DDR is read only and host software can read data from incoming DSI frames Table 30 21 DSPI_ASDR field description Field Descriptions 0 31 ASER_DATA 0 31 Alternate Serialized Data The ASER_...

Page 1283: ...19 20 21 22 23 24 25 26 27 28 29 30 31 R DESER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 21 DSPI Deserialization Data Register DSPI_DDR Table 30 23 DSPI_DDR field description Field Descr...

Page 1284: ...14 DSE1 Data Select Enable1 When TBSC bit is set the DSE1 bit controls insertion of the zero bit Data Select in the middle of the data frame The insertion bit position is defined by FMSZ field of DSPI...

Page 1285: ...from Parallel Input When the IPS0 is equal 1 the bit 0 in the frame is taken from Parallel Input and etc Please note that the DSPI_PISR0 3 only preselect Parallel Input pins final selection to the tr...

Page 1286: ...frame bit IPS Input Pin Select The IPS field selects Parallel Input pin for transmitted frame bit IPS Input Pin Select The IPS field selects Parallel Input pin for transmitted frame bit IPS Input Pin...

Page 1287: ...0 0 0 0 0 0 0 0 0 Figure 30 26 DSPI DSI Parallel Input Select Register 2 DSPI_PISR2 Table 30 28 DSPI_PISR2 Field Descriptions Field Description IPS Input Pin Select The IPS field selects Parallel Inpu...

Page 1288: ...DSPI_PISR3 Field Descriptions Field Description IPS Input Pin Select The IPS field selects Parallel Input pin for transmitted frame bit IPS Input Pin Select The IPS field selects Parallel Input pin fo...

Page 1289: ...0 0 0 0 0 Figure 30 28 DSPI DSI Deserialized Data Interrupt Mask Register DSPI_DIMR Table 30 30 DSPI_DIMR Field Descriptions Field Description MASK MASK The MASK bits define which bits in received des...

Page 1290: ...The SPI configuration allows to select which DSPI_CTAR to use on a frame by frame basis by setting a field in the SPI command The DSI configuration statically selects which DSPI_CTAR to use In CSI co...

Page 1291: ...ions are true DSPI_SR EOQF bit is clear Device is not in the debug mode is or the DSPI_MCR FRZ bit is clear DSPI_MCR HALT bit is clear The DSPI stops transitions from RUNNING to STOPPED after the curr...

Page 1292: ...lock polarity clock phase and frame size must be set for successful communication with a SPI master The SPI slave mode transfer attributes are set in the DSPI_CTAR0 30 9 2 3 FIFO disable operation The...

Page 1293: ...id entries in the TX FIFO Every time an entry is transferred from the TX FIFO to the shift register the TX FIFO Counter decrements by one At the end of a transfer bit DSPI_SR TCF is set to indicate th...

Page 1294: ...om the empty RX FIFO is undetermined When the RX FIFO is not empty the RX FIFO Drain Flag RFDF in the DSPI_SR is set The RFDF bit is cleared when the RX_FIFO is empty and the DMA controller indicates...

Page 1295: ..._ASDR as the source of the serialized data The DSPI_SDR holds the latest Parallel Input signal values which is sampled at every rising edge of the system clock The DSPI_ASDR is written by host softwar...

Page 1296: ...copied to the DSPI DSI Deserialization Data Register DSPI_DDR This register presents the deserialized data as Parallel Output signal values The DSPI_DDR is memory mapped to allow host software to rea...

Page 1297: ...Change in Data Control a transfer is initiated when the data to be serialized has changed since the transfer of the last DSI frame A copy of the previously transferred DSI data is stored in the DSPI_C...

Page 1298: ...Is to be concatenated into a single DSI frame MTO is enabled by setting the MTOE bit in the DSPI_DSICR In parallel and serial chaining there is one bus master and multiple bus slaves The bus master in...

Page 1299: ...PI modules operate as slaves The data output SOUT of the master is connected to the data input SIN of the slave The SOUT of a slave is connected to the SIN of subsequent slaves until the last block in...

Page 1300: ...signals from other slaves to the DSPI master Field DSPI_DSICR MTOCNT in DSPI_B must be written with the total number of bits to be transferred Field DSPI_DSICR MTOCNT must equal the sum of all FMSZ f...

Page 1301: ...e user must configure the DSPI so that the two DSPI_CTAR registers associated with DSI data and SPI data assert different peripheral chip select signals denoted in the figure as PCSx and PCSy The CSI...

Page 1302: ...lers and scalers 30 9 5 1 Baud rate generator The baud rate is the frequency of the Serial Communication Clock SCK The system clock is divided by a prescaler PBR and scaler BR to produce SCK with the...

Page 1303: ...field description Table 30 36 shows an example of how to compute the Delay after Transfer When in non continuous clock mode the tDT delay is configured according Equation 30 3 When in continuous clock...

Page 1304: ...ignals The SCK signal provided by the master device synchronizes shifting and sampling of the data on the SIN and SOUT pins The PCS signals serve as enable signals for the slave devices When the DSPI...

Page 1305: ...p times The DSPI can sample the incoming data later than halfway through the cycle to give the peripheral more setup time The MTFE bit in the DSPI_MCR selects between Classic SPI Format and Modified T...

Page 1306: ...data on their SOUT pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the PCS signals A delay of tDT is inserted before a new...

Page 1307: ...ormat MTFE 1 CPHA 0 In this Modified Transfer Format both the master and the slave sample later in the SCK period than in Classic SPI mode to allow tolerate more delays in device pads and board traces...

Page 1308: ...ing timing diagrams illustrate the DSPI operation with MTFE 1 Timing delays shown are Tcsc PCS to SCK assertion delay Tacs After SCK PCS negation delay Tsu_ms Master SIN setup time Thd_ms Master SIN h...

Page 1309: ...d Transfer Format MTFE 1 CPHA 0 fsck fsys 2 D0 D1 D2 Dn D0 D1 D2 Dn D0 D1 D2 Dn Slave samples SOUT SMPL_PT 2 SMPL_PT 1 DSPI samples SIN SMPL_PT 0 Tvd_sl Tsys Tcsc Tvd_sl Tasc Thd_sl Tsu_sl Thd_ms Tsu_...

Page 1310: ...he even numbered edges of SCK The master samples the slave SOUT signal on the odd numbered SCK edges starting with the third SCK edge The slave samples the last bit on the last edge of the SCK The mas...

Page 1311: ...Selection Format provides the flexibility to handle both cases The Continuous Selection Format is enabled for the SPI configuration by setting the CONT bit in the SPI command Continuous Selection is e...

Page 1312: ...CPHA 1 CONT 0 When the CONT bit 1 the PCS signal remains asserted for the duration of the two transfers The Delay between Transfers tDT is not inserted between the transfers Figure 30 47 shows the ti...

Page 1313: ...s set Continuous SCK is supported for Modified Transfer Format Clock and transfer attributes for the Continuous SCK mode are set according to the following rules The TX FIFO must be cleared before ini...

Page 1314: ...an continue with PCS asserted but with no data being shifted out of SOUT SOUT pulled high This can cause the slave to receive incorrect data Those conditions include Continuous SCK with CONT bit set b...

Page 1315: ...DSPI is able to send from 4 to 34 bits MSC data frames 4 to 32 serialized data bits and up to 2 Data Selection zero bits The serialized data bits source can be either the DSPI DSI Alternate Serializa...

Page 1316: ...1 can be implemented by software To comply with MSC specification set DSPI_CTARn LSBFE to transmit the least significant bit first Regardless of the LSBFE bit setting the Data Frame Selection Bits if...

Page 1317: ...the same data size frame without the parity check Parity can be selected as odd or even Parity Errors in the received frame set Parity Error flags in the Status register The Parity Error Interrupt Re...

Page 1318: ...rity error occurs for received DSI frame the DSPI_SR DPEF bit is set To resume DSI operation clear the DSPI_SR DPEF bit 30 9 10 Interrupts DMA requests The DSPI has several conditions that can generat...

Page 1319: ...IFO Underflow Request indicates that an underflow condition in the TX FIFO has occurred The transmit underflow condition is detected only for the DSPI operating in slave mode and SPI configuration The...

Page 1320: ...DSPI can use a FIFO buffering mechanism to transmit and receive commands and data to and from external devices The Transmit FIFO buffers SPI commands and data to be transferred The Receive FIFO buffer...

Page 1321: ...esired The PCSS signal provides the appropriate timing to enable and disable the demultiplexer for the DSPI_x_PCS 0 7 signals Figure 30 54 shows how an external 8 to 256 demultiplexer on board decoder...

Page 1322: ...urred and that data may be lost The Receive FIFO Overflow Flag is asserted when the RX FIFO is full a new frame has been received in the shift register and a transfer is initiated 30 9 15 Modified SPI...

Page 1323: ...al interrupt requests 30 9 17 1 DSPI_B connectivity The DSPI_B connects to the eMIOS eTPU_A and SIU as shown in Figure 30 56 Figure 30 56 DSPI_B connectivity Table 30 42 lists the DSPI_B connections T...

Page 1324: ...ut 1 on IMUX for External IRQ 5 6 eMIOS Output Channel 4 eTPU_A Output Channel 17 GPDO356 6 Input 1 on IMUX for External IRQ 6 7 eMIOS Output Channel 3 eTPU_A Output Channel 16 GPDO357 7 Input 1 on IM...

Page 1325: ...eTPU_A Output Channel 14 GPDO368 18 NC 19 eMIOS Output Channel 13 eTPU_A Output Channel 15 GPDO369 19 NC 20 eMIOS Output Channel 12 eTPU_A Output Channel 0 GPDO370 20 NC 21 eMIOS Output Channel 11 eT...

Page 1326: ...S Output Channel 2 eTPU_A Output Channel 9 GPDO379 29 NC 30 eMIOS Output Channel 1 eTPU_A Output Channel 10 GPDO380 30 NC 31 eMIOS Output Channel 0 eTPU_A Output Channel 11 GPDO381 31 NC Table 30 42 D...

Page 1327: ...or External IRQ 2 4 eMIOS Output Channel 19 eMIOS Output Channel 23 eTPU_A Output Channel 0 GPDO386 4 Input 2 on IMUX for External IRQ 3 5 eMIOS Output Channel 20 eMIOS Output Channel 0 eTPU_A Output...

Page 1328: ...nel 0 eTPU_A Output Channel 23 GPDO398 16 NC 17 eMIOS Output Channel 1 eTPU_A Output Channel 22 GPDO399 17 NC 18 eMIOS Output Channel 2 eTPU_A Output Channel 21 GPDO400 18 NC 19 eMIOS Output Channel 3...

Page 1329: ...PDO408 26 NC 27 eMIOS Output Channel 12 eTPU_A Output Channel 26 GPDO409 27 NC 28 eMIOS Output Channel 13 eTPU_A Output Channel 25 GPDO410 28 NC 29 eMIOS Output Channel 14 eTPU_A Output Channel 24 GPD...

Page 1330: ...accessible The states of the interrupt and DMA request signals cannot be changed while in External Stop mode Table 30 44 DSPI_D connectivity table DSPI_D input Connected to DSPI_D output Connected to...

Page 1331: ...signals cannot be cleared while in the module disable mode 30 10 Initialization Application information 30 10 1 How to manage DSPI queues The queues are not part of the DSPI but the DSPI includes fea...

Page 1332: ...SPI_MCR MSTR and enable the DSPI by clearing DSPI_MCR HALT 30 10 3 Baud rate settings Table 30 45 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR and the...

Page 1333: ...QSPI are based on a system clock of 40MHz All delay variables below will generate the same delay or as close a possible from the DSPI 100MHz system clock that an QSPI would generate from its 40MHz sy...

Page 1334: ...59 illustrates the concept of first in and last in FIFO entries along with the FIFO Counter The TX FIFO is chosen for the illustration but the concepts carry over to the RX FIFO See Section 30 9 2 4...

Page 1335: ...ddress calculation for the first in entry and last in entry in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the following equation Eqn 30 9 The memory address of...

Page 1336: ...Deserial Serial Peripheral Interface DSPI MPC5644A Microcontroller Reference Manual Rev 6 1336 Freescale Semiconductor...

Page 1337: ...cument 31 1 3 Glossary Table 31 1 Acronyms and abbreviations Term Description eSCI Enhanced SCI block with LIN support and DMA support SCI Serial Communications Interface LIN Local Interconnect Networ...

Page 1338: ...tity that consists of the start bit followed by payload bits followed by one ore more stop bits LIN byte field Special instance of a frame SCI frame Special instance of a frame LIN frame Sequence of b...

Page 1339: ...mitter and receiver Two receiver wake up methods Idle line wake up Address mark wake up Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiver full Idle receiver...

Page 1340: ...ts related interrupt enable is 0 To ensure that the module goes idle the application should clear all interrupt enable bits before triggering the mode change 31 1 6 2 SCI mode The SCI mode is the defa...

Page 1341: ...Interrupt Flag and Status Register 2 eSCI_IFSR2 0x000C LIN Control Register 1 eSCI_LCR1 LIN Control Register 2 eSCI_LCR2 0x0010 LIN transmit register eSCI_LTR Reserved 0x0014 LIN receive register eSCI...

Page 1342: ...ccess to only the lower byte of this register eSCI_BRR updates the lower byte and copies the content of the shadow register into the upper byte A byte write access to only the lower byte of this regis...

Page 1343: ...trol bit together with the M2 bit of the Control register 3 eSCI_CR3 controls the frame format used The supported frame formats and the related settings are defines in Section 31 4 2 Frame formats WAK...

Page 1344: ...d in Section 31 4 5 3 1 Receiver states and transitions 0 Receiver disabled 1 Receiver enabled RWU Receiver Wake Up Mode This bit controls and indicates the receiver wake up mode which is described in...

Page 1345: ...DMA requests generated regardless of bit errors or physical bus errors 1 Transmit DMA requests are not generated if eSCI_SR BERR flag or eSCI_SR PBERR flags are set Note This bit is used in LIN mode o...

Page 1346: ...ity Bit Masking This bit defines whether the received parity bit is presented in the related bit position in the SCI data register eSCI_DR 0 The received parity bit is presented in the bit position re...

Page 1347: ...ster 3 eSCI_CR3 during the reception of the frame presented in SCI data register eSCI_DR In case of an overrun error for subsequent frames this bit is set too 0 None of the selected errors occured 1 A...

Page 1348: ...of a received frame was transferred into the SCI data register eSCI_DR or LIN receive register eSCI_LRR and the receiver has detected a framing error during the reception of that frame as described in...

Page 1349: ...ule has transmitted a LIN wakeup signal frame LWAKE LIN Wake up Received Interrupt Flag This interrupt flag is set when a LIN Wake up character was received as described in Section 31 4 6 6 LIN wake u...

Page 1350: ...up 0 Write has no effect 1 Write triggers the generation of a wake up signal WUD LIN Bus Wake Up Delimiter Time This field determines how long the LIN protocol engine waits after the end of the trans...

Page 1351: ...uest generation enabled CKIE Checksum Error Interrupt Enable This bit controls the eSCI_IFSR2 CKERR interrupt request generation 0 CKERR interrupt request generation disabled 1 CKERR interrupt request...

Page 1352: ...ection 31 4 6 3 LIN TX frame generation If the application initiates an LIN RX frame i e the TD bit is set to 0 the content and usage shown in LIN transmit register eSCI_LTR LIN RX frame generation ap...

Page 1353: ...SE Checksum Enable This bit control the generation and checking of the checksum byte 0 No generation and checking of checksum byte 1 Generation and checking of checksum byte CRC CRC Enable This bit co...

Page 1354: ...ynom for generation and processing of CRC enhanced LIN frames Table 31 16 eSCI_LPR field descriptions Field Description P Polynomial bit xP n Used to define the LIN polynomial Reset value results in x...

Page 1355: ...error detection 1 eSCI_DR ERR flag is set on parity error detection for the data provided in eSCI_DR 0 M2 Frame Format Mode 2 This control bit together with the M bit of the Control register 1 eSCI_C...

Page 1356: ...and idle characters 31 4 2 1 Data frame formats Each data frame contains a character that is surrounded by a start bit an optional parity or address bit and one or two stop bits The supported data fra...

Page 1357: ...Formats 2 stop bits Table 31 19 Supported Data Frame Formats for RX only Control Frame Content eSCI_CR3 eSCI_CR1 Start Bits Payload Bits Stop Bits M2 M PE WAKE Character Bits Address Bits Parity Bits...

Page 1358: ...ure and content of the LIN break symbols is shown in Figure 31 20 Figure 31 20 LIN Break Symbol Format The structure and content of the SCI break characters is shown in Figure 31 21 Table 31 20 Suppor...

Page 1359: ...BRR determines the module clock divisor The baud rate clock is synchronized with the bus clock and drives the receiver The baud rate clock divided by 16 drives the transmitter The receiver has an acqu...

Page 1360: ...rator The baud rate generator is controlled by the value of the SBR field in the Baud Rate Register eSCI_BRR The frequency of the transmitter clock is determined by Equation 31 1 and defines the lengt...

Page 1361: ...a logic zero 31 4 4 1 Faster receiver tolerance In this case the receiver has a higher baud rate than the transmitter thus the stop bit sampling starts already in the last transmitted payload bit To...

Page 1362: ...n be calculated with the assumption that RS11 is sampled in the transmitted start bit and RS10 is sampled in the last stop bit For an frame with n payload bits and s stop bits the transmitter starts t...

Page 1363: ...ect frame format Control register 1 eSCI_CR1 M Control register 1 eSCI_CR1 PE Control register 1 eSCI_CR1 WAKE Control register 3 eSCI_CR3 M2 select parity type Control register 1 eSCI_CR1 PT 31 4 5 2...

Page 1364: ...7 are triggered when the described condition or event occurs The send break bit SBK in the Control register 1 eSCI_CR1 is check for the start condition The internal commit bit iCMT the transmitter act...

Page 1365: ...transmitter shift register then shifts a frame out through the TXD output signal which is prefaced with a start bit and appended with the parity bit if configured and the configured number of stop bit...

Page 1366: ...of SCI data register eSCI_DR triggers no internal operation The application request the eSCI module to enter this mode by setting the TXDMA bit in the Control register 2 eSCI_CR2 From this point in t...

Page 1367: ...ns set the transmitter continues to send break characters When the application has cleared the SBK bit or has disabled the transmitter the transmitter continues to transmit the current break character...

Page 1368: ...e receiver is changed as shown in Figure 31 27 and the action given in Table 31 30 is executed The module transitions shown in Table 31 31 are triggered when the described event occurs Table 31 29 Rec...

Page 1369: ...wire mode In Single Wire Mode the RXD pin is disconnected from the eSCI module and the TXD pin is used for both receiving and transmitting Figure 31 29 Single Wire Mode Table 31 31 Receiver Module Tra...

Page 1370: ...acter causes at least a framing error The error reporting is performed as described in Section 31 4 5 4 Reception error reporting 31 4 5 3 8 Idle character detection The Idle character detection start...

Page 1371: ...riggers the reception of new data The read access from the SCI data register eSCI_DR triggers no internal action The application request the eSCI module to enter this mode by setting the RXDMA bit in...

Page 1372: ...rresponding flags will be set 31 4 5 3 13 Bit sampling The receiver samples the selected receiver input see Section 31 4 5 3 2 Receiver input mode selection with the receiver clock RCLK The bit sampli...

Page 1373: ...verification After the successful start bit qualification the receiver starts to verify the start bit by a two out of three samples majority voting A start bit is verified if at least two out of the...

Page 1374: ...detects the number of data bit according to the selected frame format If noise is detected the noise flag eSCI_IFSR1 NF is set Table 31 33 Start Bit Noise Detection RSC8 RSC9 RSC10 Noise Detected 000...

Page 1375: ...ity error is detected this is reported as described in Section 31 4 5 4 Reception error reporting 31 4 5 4 Reception error reporting The receiver can detect four error types parity errors framing erro...

Page 1376: ...the address mark wake up pattern 31 4 5 5 1 Idle Line wake up The idle line wake up mode is selected when the WAKE bit in Control register 1 eSCI_CR1 is 0 In this mode the receiver leaves the wake up...

Page 1377: ...he connected LIN slaves and the current application enable LIN Mode LIN Control Register 1 eSCI_LCR1 LIN 1 select RXD pin as receiver input Control register 1 eSCI_CR1 LOOPS 0 Control register 1 eSCI_...

Page 1378: ...if at least one of the following conditions is fulfilled 1 the receiver is disabled eSCI_CR1 RE 0 or 2 the LIN task is in reset eSCI_LCR1 LRES 1 or 3 the start bit verification fails at sample 7 acco...

Page 1379: ...SCI_LTR provides the Identifier and Identifier Parity fields The second data written defines the number of data bytes to be transmitted The third data written defines the CRC and checksum generation T...

Page 1380: ...N transmit register eSCI_LTR and retrieves the received data by subsequent CPU read accesses to the LIN receive register eSCI_LRR In the DMA controlled mode the DMA controller provides the required fr...

Page 1381: ...register eSCI_LRR The CRC and Checksum checking is performed internally In case of errors they will be reported as described in Section 31 4 6 5 LIN error reporting After the reception of the checksu...

Page 1382: ...RXRDY flag will also be set the LINRX register must be read before normal operations can proceed 31 4 6 5 3 Standard bit error detection The standard bit error detection is enabled when the fast bit...

Page 1383: ...be set To adjust to different bus loads the sample point at which the incoming bit is compared to the one which was transmitted can be selected with the BESM bit in the Control register 2 eSCI_CR2 If...

Page 1384: ...TFRAME_MAX when a LIN RX frame is initiated 31 4 6 5 6 Checksum error detection If the checksum enable bit CSE in the LIN transmit register eSCI_LTR was set the checksum checking is performed based o...

Page 1385: ...started or running during the reception above If a LIN wake up request has been detected the LIN wake up flag LWAKE in the Interrupt Flag and Status Register 2 eSCI_IFSR2 will be set after the recepti...

Page 1386: ...set to 1 Otherwise the interrupt line is deasserted Table 31 36 eSCI Interrupt Flags and Interrupt Enable Bits Interrupt Source Operational Mode Interrupt Flag Interrupt Enable Bit Transmitter SCI eS...

Page 1387: ...it which requests the data transmission 2 wait until TDRE in Interrupt Flag and Status Register 1 eSCI_IFSR1 is set this indicates the start of transmission the iCMT bit was cleared 3 clear and subseq...

Page 1388: ...Enhanced Serial Communication Interface ESCI MPC5644A Microcontroller Reference Manual Rev 6 1388 Freescale Semiconductor...

Page 1389: ...ovides a differentiation between Supervisor and User access types all accesses will be always considered of the Supervisor type As a consequence the SUPV bit in the Module Configuration Register MCR R...

Page 1390: ...FEN Tq 0 1 Bus Off Error Tx Warning Rx Warning Wake up N N 1 1 1 1 1 1 CR ERRMSK CR BOFFMSK CR TWRNMSK CR RWRNMSK MCR WAK_MSK N IMRH IMRL BUFFxM Message Buffer Interrupts Notes 1 Pins can be configura...

Page 1391: ...les Message Buffer selection for reception and transmission taking care of arbitration and ID matching algorithms The Bus Interface Unit BIU submodule controls the access to and from the internal inte...

Page 1392: ...ral purpose RAM space Listen only mode capability Programmable loop back mode supporting self test operation Programmable transmission priority scheme lowest ID lowest buffer number or highest priorit...

Page 1393: ...ensure proper reception of its own message Both transmit and receive interrupts are generated Module Disable Mode This low power mode is entered when the MDIS bit in the MCR Register is asserted by th...

Page 1394: ...idual register is identified by its complete name and the corresponding mnemonic The access type can be Supervisor S or Unrestricted U Most of the registers can be configured to have either Supervisor...

Page 1395: ...x Buffer 15 Mask RX15MASK S U Yes No Base 0x001C Error Counter Register ECR S U Yes Yes Base 0x0020 Error and Status Register ESR S U Yes Yes Base 0x0024 Interrupt Masks 2 IMRH S U Yes Yes Base 0x0028...

Page 1396: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1396 Freescale Semiconductor 32 4 2 Message buffer architecture The message buffer architecture is shown in Figure 32 3...

Page 1397: ...lgorithm Device Peripheral Bus Move data Scan buffers CAN Engine CANTX CANRX 1 1 Protocol Engine Rx Serial Message Buffer Data Data Length ID No queuing Queuing Rx ID Matching Rx ID Matching used algo...

Page 1398: ...Section 32 5 Functional description for additional information SRR Substitute Remote Request Fixed recessive bit used only in extended format It must be set to 1 by the user for transmission Tx Buffe...

Page 1399: ...nificant bits 3 to 13 are used for frame identification in both receive and transmit cases The 18 least significant bits are ignored In Extended Frame format all bits are used for frame identification...

Page 1400: ...sserted MB does not participate in the arbitration process 0 1100 1000 Transmit data frame unconditionally once After transmission the MB automatically returns to the INACTIVE state 1 1100 0100 Transm...

Page 1401: ...ontains an 8 entry ID table that specifies filtering criteria for accepting frames into the FIFO Figure 32 6 shows the three different formats that the elements of the ID table can assume depending on...

Page 1402: ...ch the target ID 1 Extended frames can be accepted and standard frames are rejected 0 Extended frames are rejected and standard frames can be accepted RXIDA Rx Frame Identifier Format A Specifies an I...

Page 1403: ...1 1 0 0 1 1 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 LPRIO_EN AEN 0 0 IDAM 0 0 MAXMB W RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Unimplemented or Reserved Table 32 8 Module Con...

Page 1404: ...ther in Normal Mode Listen Only Mode or Loop Back Mode WAK_MSK Wake Up Interrupt Mask This bit enables the Wake Up Interrupt generation 1 Wake Up Interrupt is enabled 0 Wake Up Interrupt is disabled S...

Page 1405: ...ture when FlexCAN is in Stop Mode If this bit had been asserted by the time FlexCAN entered Stop Mode then FlexCAN will look for a recessive to dominant transition on the bus during these modes If a t...

Page 1406: ...lexCAN uses its previous masking scheme with RXGMASK RX14MASK and RX15MASK The reception queue feature is disabled Upon receiving a message if the first message buffer with a matching ID that is found...

Page 1407: ...ments of the table are configured at the same time by this field they are all the same format See Section 32 4 4 Rx FIFO structure MAXMB Maximum Number of Message Buffers This 6 bit field defines the...

Page 1408: ...protocol For the reset value the Sclock frequency is equal to the CPI clock frequency The maximum value of this register is 0xFF that gives a minimum Sclock frequency equal to the CPI clock frequency...

Page 1409: ...f MCR WRNEN is negated and it is read as zero when MCR WRNEN is negated 1 Tx Warning Interrupt enabled 0 Tx Warning Interrupt disabled RWRNMSK Rx Warning Interrupt Mask This bit provides a mask for th...

Page 1410: ...tate disabled 0 Automatic recovering from Bus Off state enabled according to CAN Spec 2 0 part B TSYN Timer Sync Mode This bit enables a mechanism that resets the free running timer each time a messag...

Page 1411: ...ata will take some time to be actually written to the register If desired software can poll the register to discover when the data was actually written Figure 32 9 Free Running Timer TIMER 32 4 5 4 Rx...

Page 1412: ...per message buffer setting MCR MBFEN causes the RX15MASK Register to have no effect on the module operation When MCR MBFEN is negated RX15MASK is used as acceptance mask for the Identifier in Message...

Page 1413: ...If the FlexCAN state is Error Passive and either TXECNT or RXECNT decrements to a value less than or equal to 127 while the other already satisfies this condition ESR FLTCONF is updated to reflect Err...

Page 1414: ...e interrupt flags that can be cleared by writing 1 to them writing 0 has no effect See Section 32 5 10 Interrupts for more details Figure 32 12 Error and Status Register ESR Base 0x001C 0 1 2 3 4 5 6...

Page 1415: ...the transmitted and the received bit in a message 1 At least one bit sent as recessive is received as dominant 0 No such occurrence Note This bit is not set by a transmitter in case of arbitration fie...

Page 1416: ...AN is transmitting or receiving a message when the CAN bus is not in IDLE state This bit has no meaning when IDLE is asserted 1 FlexCAN is transmitting a message IDLE 0 0 FlexCAN is receiving a messag...

Page 1417: ...is set an interrupt is generated to the CPU This bit is cleared by writing it to 1 Writing 0 has no effect 1 Indicates a recessive to dominant transition received on the CAN bus when the FlexCAN modu...

Page 1418: ...0 has no effect When MCR AEN is set Abort enabled while the IFRH bit is set for a message buffer configured as Tx the writing access done by CPU into the corresponding message buffer will be blocked...

Page 1419: ...ed Figure 32 16 Interrupt Flags 1 Register IFRL Base 0x002C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF 63I BUF 62I BUF 61I BUF 60I BUF 59I BUF 58I BUF 57I BUF 56I BUF 55I BUF 54I BUF 53I BUF 52I BUF...

Page 1420: ...e respective FlexCAN Message Buffer MB8 to MB31 interrupt 1 The corresponding message buffer has successfully completed transmission or reception 0 No such occurrence BUF7I Buffer MB7 Interrupt or FIF...

Page 1421: ...message buffers to be transmitted based on the message ID optionally augmented by three local priority bits or the message buffer ordering Before proceeding with the functional description an importa...

Page 1422: ...pt Flag be negated by CPU It means that the CPU must clear the corresponding IFRL or IFRH register before starting to prepare this message buffer for a new transmission or reception 32 5 3 Arbitration...

Page 1423: ...ion write an ABORT code 1001 to the Code field of the Control and Status word to request an abortion of the transmission then read back the Code field and the IFRL or IFRH register to check if the tra...

Page 1424: ...olling by reading directly the C S word of the message buffers Instead read the corresponding IFRL or IFRH register Note that the received ID field is always stored in the matching message buffer thus...

Page 1425: ...arrives the matching algorithm will find the first match in MB number 2 The code of this message buffer is EMPTY so the message is stored there When the second message arrives the matching algorithm...

Page 1426: ...the SMB for transmission the write operation is blocked and the message buffer is not deactivated but the abort request is captured and kept pending until one of the following conditions are satisfied...

Page 1427: ...e coherent therefore deactivation of that message buffer is done Even with the coherence mechanism described above writing to the Control and Status word of active message buffers when not in Freeze M...

Page 1428: ...emain in the SMB waiting for the message buffer to be unlocked and only then will be written to the message buffer If the message buffer is not unlocked in time and yet another new message with the sa...

Page 1429: ...formats see also Section 32 4 4 Rx FIFO structure Format A 8 extended or standard IDs including IDE and RTR Format B 16 standard IDs or 16 extended 14 bit ID slices including IDE and RTR Format C 32...

Page 1430: ...bitration process but is considered as normal Tx message buffer with no higher priority The data length of this frame is independent of the DLC field in the remote frame that initiated its transmissio...

Page 1431: ...le operation the clock source should be selected while the module is in Disable Mode bit MDIS set in the Module Configuration Register Figure 32 18 CAN engine clocking scheme The crystal oscillator cl...

Page 1432: ...G2 field of the CR Register plus 1 to be 2 to 8 time quanta long Figure 32 19 Segments within the Bit Time Table 32 20 gives an overview of the CAN compliant segment settings and the related parameter...

Page 1433: ...atching and arbitration FlexCAN needs to scan the whole Message Buffer memory during the available time slot In order to have sufficient time to do that the following requirements must be observed A v...

Page 1434: ...to Debug Mode In both cases it is also necessary that MCR FRZ is asserted and the module is not in either of the low power modes Disable or Stop When Freeze Mode is requested during transmission or re...

Page 1435: ...AN receives the global Stop Mode request during Freeze Mode it sets MCR MDISACK negates MCR FRZACK and then sends a Stop Acknowledge signal to the CPU in order to shut down the clocks globally If Stop...

Page 1436: ...ion reception and is cleared when the CPU writes it to 1 unless another interrupt is generated at the same time NOTE It must be guaranteed that the CPU only clears the bit causing the current interrup...

Page 1437: ...comes one The message buffer memory starts at 0x0060 but the space from 0x0060 to 0x007F is reserved for SMB usage and the space from 0x0080 to 0x008F is used by the one message buffer This leaves us...

Page 1438: ...ning interrupts by setting the WRNEN bit If required disable frame self reception by setting the SRX_DIS bit Enable the FIFO by setting the FEN bit Enable the abort mechanism by setting the AEN bit En...

Page 1439: ...memory and 256 bytes for Individual Mask Registers In each configuration the user can program the maximum number of message buffers that will take part in the matching and arbitration processes using...

Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...

Page 1441: ...Controller Module described in this chapter CDC Clock Domain Crosser CHI Controller Host Interface Cycle length in T The actual length of a cycle in T for the ideal CC 0 ppm EBI External Bus Interface...

Page 1442: ...ost interface CHI Protocol engine PE Clock domain crossing unit CDC A block diagram of the CC with its surrounding modules is given in Figure 33 1 MCU Microcontroller Unit T Microtick MT Macrotick MTS...

Page 1443: ...or asynchronous PE and CHI clock domains The CC stores the frame header and payload data of frames received or of frames to be transmitted in the FlexRay memory area The application accesses the FlexR...

Page 1444: ...mory area Allows for flexible and efficient message buffer implementation Consistent data access ensured by means of buffer locking scheme Application can lock multiple buffers at the same time Size o...

Page 1445: ...to absolute or relative SECDED for protocol engine data RAM SEDDED for CHI lookup table RAM 33 1 6 Modes of operation This section describes the basic operational power modes of the CC 33 1 6 1 Disabl...

Page 1446: ...s connected to external pins These signals are summarized in Table 33 2 and described in detail in Section 33 2 1 Detailed signal descriptions NOTE The off chip signals FR_A_RX FR_A_TX and FR_A_TX_EN...

Page 1447: ...FR_DBG 1 FR_DBG 0 Strobe Signals These signals provide the selected debug strobe signals For details on the debug strobe signal selection refer to Section 33 6 16 Strobe signal support 33 3 Controlle...

Page 1448: ...s defined by the memory map of the MCU 33 5 1 Memory map The complete memory map of the CC is shown in Table 33 3 The addresses presented here are the offsets relative to the CC base address which is...

Page 1449: ...r Flag Register FR_CHIERFR R W on page 33 1474 0x0022 Message Buffer Interrupt Vector Register FR_MBIVEC R on page 33 1476 0x0024 Channel A Status Error Counter Register FR_CASERCR R on page 33 1477 0...

Page 1450: ...0x0046 Sync Frame ID Rejection Filter Register FR_SFIDRFR R W on page 33 1491 0x0048 Sync Frame ID Acceptance Filter Value Register FR_SFIDAFVR R W on page 33 1492 0x004A Sync Frame ID Acceptance Filt...

Page 1451: ...CCR R W on page 33 1498 Slot Status 0x0068 Slot Status Register 0 FR_SSR0 R on page 33 1500 0x006A Slot Status Register 1 FR_SSR1 R on page 33 1500 0x006C Slot Status Register 2 FR_SSR2 R on page 33 1...

Page 1452: ...507 0x008E Receive FIFO B Read Index Register FR_RFBRIR R on page 33 1507 Receive FIFO Filter 0x0090 Receive FIFO Message ID Acceptance Filter Value Register FR_RFMIDAFVR R W on page 33 1508 0x0092 Re...

Page 1453: ...page 33 1505 Receive FIFO Control cont 0x00EE Receive FIFO Fill Level and POP Count Register FR_RFFLPCR R W on page 33 1508 ECC Registers 0x00F0 ECC Error Interrupt Flag and Enable Register FR_EEIFER...

Page 1454: ...SR127 R W on page 33 1527 0x04FA Message Buffer Cycle Counter Filter Register 127 FR_MBCCFR127 R W on page 33 1529 0x04FC Message Buffer Frame ID Register 127 FR_MBFIDR127 R W on page 33 1530 0x04FE M...

Page 1455: ...tempt to this register bit or field is ignored without any notification The values of the bits or fields are not changed The condition term A or B indicates that the register or field can be written t...

Page 1456: ...ontrols the write mode If the WMD bit is set to 0 during the write access all fields of the internal register are updated If the WMD bit set to 1 only the SEL field is changed All other fields of the...

Page 1457: ...bled Mode by writing 1 to this bit Before leaving the Disabled Mode the application must configure the SCM SBFF CHB CHA TMODE BITRATE values For details see Section 33 1 6 Modes of operation 0 Write i...

Page 1458: ...ory Base Address Register FR_RFSYMBADR CLKSEL Protocol Engine Clock Source Select This bit is used to select the clock source for the protocol engine 0 PE clock source is generated by on chip crystal...

Page 1459: ...R_A_TX and FR_A_TX_EN driven by CC connected to FlexRay channel B ports FR_B_RX FR_B_TX and FR_A_TX_EN not driven by CC 1 1 Reserved Base 0x0004 Write Disabled Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 1460: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 6 Strobe Signal Control Register FR_STBSCR Table 33 11 FR_STBSCR field description Field Description WMD Write Mode This control bit defines the write mode...

Page 1461: ...rt 3 0x3 minislot start pulse 0 MT start 4 0x4 slot start A pulse 0 MT start 5 0x5 B 6 0x6 receive data after glitch filtering A value 4 FR_A_RX 7 0x7 B FR_B_RX 8 0x8 channel idle indicator A level 5...

Page 1462: ...message buffer number of the last individual message buffer that is assigned to the first message buffer segment The individual message buffers in the first segment correspond to the message buffer co...

Page 1463: ...Section 33 6 24 Memory content error detection 33 5 2 10 PE DRAM Data Register FR_PEDRDR This register provides the data to be written to or read from the PE DRAM by the access initiated by write acc...

Page 1464: ...0 0 0 0 Figure 33 11 Protocol Operation Control Register FR_POCR Table 33 16 FR_POCR field description Field Description WME Write Mode External Correction This bit controls the write mode of the EOC...

Page 1465: ...yet accepted not ready to receive new protocol command Write Mode Command This bit controls the write mode of the POCCMD field 0 Write to POCCMD field on register write 1 Do not write to POCCMD field...

Page 1466: ...A in the Protocol Status Register 3 FR_PSR3 0 No wakeup condition or interrupt disabled 1 Wakeup symbol received on FlexRay bus and interrupt enabled FAFBIF Receive FIFO Channel B Almost Full Interrup...

Page 1467: ...Interrupt line is asserted when the PRIF flag is set 0 Disable interrupt line 1 Enable interrupt line CHIE CHI Interrupt Enable This flag controls if the CHI Interrupt line is asserted when the CHIF f...

Page 1468: ...l protocol error occurs when the protocol engine has not finished a calculation and a new calculation is requested This can be caused by a hardware error 0 No such event 1 Internal protocol error dete...

Page 1469: ...annel A or channel B 0 No such event 1 MTS symbol received LTXB_IF pLatestTx Violation on Channel B Interrupt Flag This flag is set when the frame transmission on channel B in the dynamic segment exce...

Page 1470: ...egal Protocol Control Command Interrupt Flag This flag is set when the PE tries to execute a protocol control command which was issued via the POCCMD field of the Protocol Operation Control Register F...

Page 1471: ...upt Enable Register 0 FR_PIER0 Table 33 20 FR_PIER0 field description Field Description FATL_IE Fatal Protocol Error Interrupt Enable This bit controls FATL_IF interrupt request generation 0 interrupt...

Page 1472: ...nable This bit controls LTXA_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled TBVB_IE Transmission across boundary on channel B Interrupt...

Page 1473: ...bit controls IPC_IF interrupt request generation 0 interrupt request generation disabled 1 interrupt request generation enabled PECF_IE Protocol Engine Communication Failure Interrupt Enable This bit...

Page 1474: ...rame Lost Channel A Error Flag This flag is set if a complete frame was received on channel A but could not be stored in the selected individual message buffer because this message buffer is currently...

Page 1475: ...not grant the lock to the transmit side of a double transmit message buffer 0 No such event 1 Double transmit buffer lock error occurred SBCF_EF System Bus Communication Failure Error Flag This flag i...

Page 1476: ...Management Vector Registers FR_NMVR0 FR_NMVR5 are not updated 0 No such error occurred 1 Network management frame error occurred ILSA_EF Illegal System Bus Address Error Flag This flag is set if the e...

Page 1477: ...ocol related error indicator bits vSS SyntaxError vSS ContentError vSS BViolation and vSS TxConflict The CC increments the status error counter by 1 if for a slot or segment at least one error indicat...

Page 1478: ..._PSR0 Table 33 26 FR_PSR0 field description Field Description ERRMODE Error Mode protocol related variable vPOC ErrorMode This field indicates the error mode of the protocol 00 ACTIVE 01 PASSIVE 10 CO...

Page 1479: ...0 POC coldstart consistency check 1011 Reserved 1100 Reserved 1101 POC integration coldstart check 1110 POC coldstart gap 1111 POC coldstart join WAKEUP STATUS Wakeup Status protocol related variable...

Page 1480: ...such event 1 POC normal active state was reached from POC startup state via noisy leading cold start path HHR Host Halt Request Pending protocol related variable vPOC CHIHaltRequest This status bit i...

Page 1481: ...Conflict for symbol window on channel B This status bit is set if there was a transmission conflict during the symbol window on channel B 0 No such event 1 Transmission conflict detected SBVB Symbol W...

Page 1482: ...ring the symbol window on channel A 0 No such event 1 Syntax error detected MTA Media Access Test Symbol MTS Received on Channel A protocol related variable vSS ValidMTS for symbol window on channel A...

Page 1483: ...when a syntax error has been detected on channel B Syntax errors are detected in the communication slots the symbol window and the NIT 0 No syntax error detected 1 Syntax errors detected AVFB Aggrega...

Page 1484: ...gh channel A 0 No syntactically valid frames received 1 At least one syntactically valid frame received Base 0x0030 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 MTCT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1485: ...15 R 0 0 0 0 0 SLOTCNTA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 27 Slot Counter Channel A Register FR_SLTCTAR Table 33 32 FR_SLTCTAR field description Field Description SLOTCNTA Slot Counter...

Page 1486: ...upt Flag Register 0 FR_PIFR0 Note If the CC was not able to calculate a new rate correction term due to a lack of synchronization frames the RATECORR value is not updated Base 0x003A Additional Reset...

Page 1487: ...MIF PRIF CHIF WUPIF FAFBIF FAFAIF RBIF TBIF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 31 Combined Interrupt Flag Register FR_CIFR Table 33 36 FR_CIFR field description Field Description MIF Mo...

Page 1488: ...buffers has the MBIF flag asserted TBIF Transmit Message Buffer Interrupt Flag This flag is set if for at least one of the individual single or double transmit message buffers FR_MBCCSRn MTD 1 the int...

Page 1489: ...ated variable size of vsSyncIdListA for even cycle This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization SFODB Sync Frames Ch...

Page 1490: ...ables CYCNUM Cycle Number This field provides the number of the cycle in which the currently locked table was recorded If none or both tables are locked this value is related to the even cycle table E...

Page 1491: ...pair of enabled Sync Frame Tables into FlexRay memory area SDVEN Sync Frame Deviation Table Enable This bit controls the generation of the Sync Frame Deviation Tables The application must set this bit...

Page 1492: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 37 Sync Frame ID Acceptance Filter Value Register FR_SFIDAFVR Table 33 42 FR_SFIDAFVR field description Field Description FVAL Filter Value This field defines th...

Page 1493: ...efines the length of the network management vector in bytes Table 33 44 NMVR 0 5 field description Field Description NMVP Network Management Vector Part The mapping between the Network Management Vect...

Page 1494: ...er T2 Configuration This bit configures the timebase mode of Timer T2 0 T2 is absolute timer 1 T2 is relative timer T2_REP Timer T2 Repetitive Mode This bit configures the repetition mode of Timer T2...

Page 1495: ...is register holds the macrotick offset value for timer T1 For a detailed description of timer T1 refer to Section 33 6 17 1 Absolute timer T1 Base 0x005C Write Anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 1496: ...mmediately and timer T2 will expire according to the changed values If timer T2 is configured as a relative timer and the application changes the values in this register while the timer is running the...

Page 1497: ...on Register FR_SSSR This register is used to access the four internal non memory mapped slot status selection registers FR_SSSR0 to FR_SSSR3 Each internal registers selects a slot or symbol window NIT...

Page 1498: ...r access 00 select FR_SSSR0 01 select FR_SSSR1 10 select FR_SSSR2 11 select FR_SSSR3 SLOTNUMBER Slot Number This field specifies the number of the slot whose status will be saved in the corresponding...

Page 1499: ...n cycle only 1 The Slot Status Counter accumulates over multiple communication cycles VFR Valid Frame Restriction This bit is used to restrict the counter to received valid frames 0 The counter is not...

Page 1500: ...Base 0x0068 FR_SSR0 Base 0x006A FR_SSR1 Base 0x006C FR_SSR2 Base 0x006E FR_SSR3 Base 0x0070 FR_SSR4 Base 0x0072 FR_SSR5 Base 0x0074 FR_SSR6 Base 0x0076 FR_SSR7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 1501: ...col related variable vRF Header SyFIndicator channel A 0 vRF Header SyFIndicator 0 1 vRF Header SyFIndicator 1 NFA Null Frame Indicator Channel A protocol related variable vRF Header NFIndicator chann...

Page 1502: ...FR_SSCCRn MCY bit and waiting for the next cycle start when the CC clears the counter Subsequently the counter can be set into the multicycle mode again 33 5 2 50 MTS A Configuration Register FR_MTSA...

Page 1503: ...Counter Mask This field provides the filter mask for the MTS cycle count filter CYCCNTVAL Cycle Counter Value This field provides the filter value for the MTS cycle count filter Base 0x0082 Write MTE...

Page 1504: ...channel B segment 2 RSBIDX Receive Shadow Buffer Index This field contains the current index of the message buffer header field of the receive shadow message buffer selected by the SEL field The CC us...

Page 1505: ...Description PTD Periodic Timer Duration This value defines the periodic timer duration in terms of macroticks 0000 timer stays expired 3FFF timer never expires other timer expires after specified num...

Page 1506: ...0 SIDXA SIDXB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 57 Receive FIFO Start Index Register FR_RFSIR Table 33 65 FR_RFSIR field description Field Description SIDXA SIDXB Start Index This fiel...

Page 1507: ...67 FR_RFARIR field description Field Description RDIDX Read Index This field provides the message buffer header index of the next available FIFO message buffer that the application can read If the ol...

Page 1508: ...lue for the message ID acceptance filter of the selected FIFO For details on message ID filtering see Section 33 6 9 9 FIFO filtering Base 0x00EE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FLB FLA W PCB...

Page 1509: ...ion MIDAFVALA MIDAFVALB Message ID Acceptance Filter Value Filter value for the message ID acceptance filter Base 0x0092 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MIDAFMSKA MIDAFMSKB W...

Page 1510: ...tion FIDRFMSK Frame ID Rejection Filter Mask Filter mask for the frame ID rejection filter Base 0x0098 16 bit write access required Write WMD IBD SEL Any Time SID POC config 0 1 2 3 4 5 6 7 8 9 10 11...

Page 1511: ...range filter 2 runs as rejection filter F1MD Range Filter 1 Mode This control bit defines the filter mode of the frame ID range filter 1 0 range filter 1 runs as acceptance filter 1 range filter 1 run...

Page 1512: ...n Version 2 1 Rev A Table 33 76 FR_LDTXSLAR field description Field Description LASTDYNTX SLOTA Last Dynamic Transmission Slot Channel A protocol related variable zLastDynTxSlot channel A Number of th...

Page 1513: ...acroInitialOffset B MT 16 macro_per_cycle gMacroPerCycle MT 10 macro_after_first_static_slot gMacroPerCycle gdStaticSlot MT 1 macro_after_offset_correction gMacroPerCycle gOffsetCorrectionStart MT 28...

Page 1514: ...rift T 26 27 micro_per_macro_nom_half round pMicroPerMacroNom 2 T 7 offset_correction_out pOffsetCorrectionOut T 9 rate_correction_out pRateCorrectionOut T 14 single_slot_enabled pSingleSlotEnabled bo...

Page 1515: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 macro_after_first_static_slot W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 71 Protocol Configuration Register 1 FR_PCR1 Base 0x00A4 Write POC config 0 1...

Page 1516: ...12 13 14 15 R 0 symbol_window_after_action_point macro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 76 Protocol Configuration Register 6 FR_PCR6 Base 0x00AE Write POC config 0 1...

Page 1517: ...ocol Configuration Register 10 FR_PCR10 Base 0x00B6 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R key_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start W Reset 0...

Page 1518: ...14 FR_PCR14 Base 0x00BE Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R listen_timeout 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 85 Protocol Configuration Register 15 FR_PCR15 Ba...

Page 1519: ...e 0x00C8 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_initial_offset_b micro_initial_offset_a W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 90 Protocol Configuration Register 20...

Page 1520: ...0x00D2 Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R micro_per_cycle_min 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 95 Protocol Configuration Register 25 FR_PCR25 Base 0x00D4 W...

Page 1521: ...33 6 24 2 Memory error reporting Base 0x00DA Write POC config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R extern_offset_ correction minislots_max W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 99 Prot...

Page 1522: ...1 b memory errors are detected but not corrected on at least two banks of the PE DRAM 0 no such event 1 Non Corrected Error overflow detected on PE DRAM DRCE_OF DRAM Corrected Error Overflow Flag This...

Page 1523: ...ine is asserted when the DRCE_IF flag is set 0 Disable interrupt line 1 Enable interrupt line Base 0x00F2 Write ERS Anytime ERM EIM EIE IDL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BSY 0 0 0 0 0 ERS 0...

Page 1524: ...is 0 Error Injection Enable bit FR_EERICR EIE should not be set to 1 Base 0x00F4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MID BANK ADDR W Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 103 ECC Error...

Page 1525: ...ure 33 104 ECC Error Report Data Register FR_EERDR Table 33 83 FR_EERDR field description Field Description DATA Data The content of this field depends on the report mode selected by FR_EERICR ERM ERM...

Page 1526: ...e ECC checkbits read from the memory Base 0x00FA Write IDL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MID BANK ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 106 ECC Error Injection Address Regis...

Page 1527: ...d by FR_EERICR EIM EIM 0 This field defines the XOR distortion pattern for the data written into the memory EIM 1 This field defines the data to be written into the memory Base 0x00FE Write IDL 0 1 2...

Page 1528: ...ansfer direction of a message buffer 0 Receive message buffer 1 Transmit message buffer Message Buffer Control CMT Commit for Transmission This bit indicates if the transmit message buffer data are re...

Page 1529: ...ssion mode of the message buffer 0 receive message buffer contains no valid frame data message is transmitted for the first time 1 receive message buffer contains valid frame data message will be tran...

Page 1530: ...g disabled 1 Cycle counter filtering enabled CCFMSK Cycle Counter Filtering Mask This field defines the filter mask for the cycle counter filtering CCFVAL Cycle Counter Filtering Value This field defi...

Page 1531: ...the FlexRay bus are stored in data structures called physical message buffers The Table 33 92 FR_MBFIDRn field description Field Description FID Frame ID The semantic of this field depends on the mess...

Page 1532: ...first six bytes in the message buffer header field It contains all FlexRay frame header related information according to the FlexRay Communications System Protocol Specification Version 2 1 Rev A A de...

Page 1533: ...sections 33 6 3 1 Individual message buffers The individual message buffers are used for all types of frame transmission and for dedicated frame reception based on individual filter settings for each...

Page 1534: ...ond segment is 2 FR_MBDSR MBSEG2DS bytes 33 6 3 2 Receive shadow buffers The receive shadow buffers are required for the frame reception process for individual message buffers The CC provides four rec...

Page 1535: ...nel A receive FIFO consists of a set of physical message buffers in the FlexRay memory area and a set of receive FIFO control registers located in dedicated registers The structure of a receive FIFO i...

Page 1536: ...33 6 3 4 1 Individual message buffer configuration data Before an individual message buffer can be used for transmission or reception it must be configured There is a set of common configuration param...

Page 1537: ...gnment The CCFE CCFMSK and CCFVAL bits and fields configure the cycle counter filter Message Buffer Frame ID Registers FR_MBFIDRn For a transmit message buffer the FID field is used to determine the s...

Page 1538: ...eceive FIFO Range Filter Configuration Register FR_RFRFCFR 33 6 3 7 2 Receive FIFO control data The application can access the FIFOs at any time using the control bits in the following registers Globa...

Page 1539: ...y memory area The FlexRay memory area consists of two contiguous regions The size of each region is maximum 64 Kbytes Each region start at a 16 byte boundary Message Buffer Header Area FlexRay Memory...

Page 1540: ...i 256 Eqn 33 6 2 The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill Equation 33 7 SADR_MBHF i 10 FR_SYMBADR SMBA 0 i 1024 Eqn 33 7 FIFO Header Area FIFO Fle...

Page 1541: ...must fulfill Equation 33 10 SADR_MBHF i 10 FR_RFSYMBADR SMBA 0 i 1024 Eqn 33 10 2 The message buffer header fields for each FIFO have to be a contiguous area 33 6 4 6 Message buffer data area The mes...

Page 1542: ...ow buffers the frame header receives the frame header data of the current frame received regardless of whether the frame is valid or not For transmit message buffers the application writes the frame h...

Page 1543: ...ame header checks As shown in Figure 33 120 and Figure 33 121 not all fields in the message buffer frame header are used for transmission Some fields in the message buffer frame header are ignored som...

Page 1544: ...of the Reserved bit of the received frame stored in the message buffer PPI Payload Preamble Indicator This is the value of the Payload Preamble Indicator of the received frame stored in the message bu...

Page 1545: ...it is not used the value of the Sync Frame Indicator is generated internally according to FlexRay Communications System Protocol Specification Version 2 1 Rev A SUF Startup Frame Indicator This bit is...

Page 1546: ...SUB SEB CEB BVB 1 0 0 0 0 0 0 0 0 Reset Table 33 98 Receive Message Buffer Slot Status field description Field Description Common Message Buffer Status Bits VFB Valid Frame on Channel B protocol relat...

Page 1547: ...is set to 0 if no valid frame was received at all in the subscribed slot 0 first valid frame received on channel A or no valid frame received at all 0 first valid frame received on channel B VFA Valid...

Page 1548: ...nd FR_MBCCFRn CHB 1 see Figure 33 127 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VFB SYB NFB SUB SEB CEB BVB TCB VFA SYA NFA SUA SEA CEA BVA TCA Reset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0...

Page 1549: ...B 0 vSS TxConflict 0 1 vSS TxConflict 1 VFA Valid Frame on Channel A protocol related variable vSS ValidFrame channel A 0 vSS ValidFrame 0 1 vSS ValidFrame 1 SYA Sync Frame Indicator Channel A protoco...

Page 1550: ...message buffer is locked the CC will not update the Message Buffer Data Field For receive FIFOs the application can read the message buffer indicated by the Receive FIFO A Read Index Register FR_RFAR...

Page 1551: ...rt of the message buffer configuration data is common to all individual message buffers and the receive shadow buffers These data can only be set when the protocol is in the POC config state Table 33...

Page 1552: ...nel with at least one individual receive message buffer assigned the application must configure the related receive shadow buffer using the Receive Shadow Buffer Index Register FR_RSBIR 33 6 6 1 2 Spe...

Page 1553: ...sage buffer with message buffer number n is configured to be a single transmit message buffer by the following settings FR_MBCCSRn MBT 0 single buffered message buffer FR_MBCCSRn MTD 1 transmit messag...

Page 1554: ...der to ensure data consistency The transmit message buffer states are given in Figure 33 130 A description of the states is given in Table 33 106 which also provides the access scheme for the access r...

Page 1555: ...access to data control and status Included in message buffer search CCSa 1 0 Slot Assigned Message buffer assigned to next static slot Ready for Null Frame transmission HLckCCSa 1 1 MSG Locked and Sl...

Page 1556: ...the POC config state for Slot 1 then the message buffer cannot be disabled in the INTEGRATION_LISTEN state by directly writing 1 to the EDT bit To facilitate this a FREEZE command needs to be issued j...

Page 1557: ...given in the second part of Table 33 109 Table 33 107 Single transmit message buffer application transitions Transition Command Condition Description HE FR_MBCCSRn EDT 1 FR_MBCCSRn EDS 0 Application...

Page 1558: ...ual message buffer search the CC triggers the message available transition MA for up to two transmit message buffers This changes the message buffer state from Idle to CCMa and the message buffers can...

Page 1559: ...ne transmit message buffer is configured with the FR_MBFIDRn FID set to S and FR_MBCCFRn CHA set to 1 A Null Frame is transmitted in the static slot S on channel A if this slot is assigned to the CC f...

Page 1560: ...3 135 Null frame transmission from HLck state with unlock Since the null frame transmission will not use the message buffer data the application can lock unlock the message buffer during null frame tr...

Page 1561: ...the end of transmission and will set the valid flag FR_MBCCSRn DVAL to indicate that the message will be transmitted again Message buffer status update after incomplete message transmission The term i...

Page 1562: ...me is implemented that is used to control the access to the data control and status bits of a message buffer The access regions for receive message buffers are depicted in Figure 33 137 A description...

Page 1563: ...er states is given in Table 33 106 which also provides the access scheme for the access regions The status bits FR_MBCCSRn EDS and FR_MBCCSRn LCKS provide the application with the required status info...

Page 1564: ...essage buffer cannot be disabled in the INTEGRATION_LISTEN state by directly writing 1 to the EDT bit To facilitate this a FREEZE command needs to be issued just before running the message buffer disa...

Page 1565: ...ediate state is CCRx and the resulting state is locked buffer subscribed state HLckCCRx Table 33 112 Receive message buffer application transitions Transition Host command Condition Description HE FR_...

Page 1566: ...uffers For details on receive shadow buffers see Section 33 6 6 3 5 Receive shadow buffers concept The data and status of the receive message buffers that are the CCRx or HLckCCRx are not modified in...

Page 1567: ...s defined by the Message Buffer Segment Size and Utilization Register FR_MBSSUTR Table 33 115 Receive message buffer update vSS ValidFrame vRF Header NFIndicator Update description 1 1 Valid non null...

Page 1568: ...s to ensure that only syntactically and semantically valid received non null frames are presented to the application in a receive message buffer The basic structure of a receive shadow buffer is descr...

Page 1569: ...o the FlexRay bus The two sides are located in adjacent individual message buffers The message buffer that implements the commit side has an even message buffer number 2n The transmit side message buf...

Page 1570: ...le Commit side CFG read write Message Buffer Configuration MSG read write Message Buffer Data and Control access ITX read write Internal Message Transfer SS write only Slot Status Update Transmit side...

Page 1571: ...the required message buffer status information The internal status information is not visible to the application 33 6 6 4 2 Message buffer states This section describes the transmit message buffer sta...

Page 1572: ...t side sheet 2 of 2 State FR_MBCCSRn Access region Description EDS LCKS Appl Module Common states HDis 0 0 CFG Disabled Message Buffer under configuration Excluded from message buffer search CCITx 1 0...

Page 1573: ...ock and Unlock The lock and unlock commands can be issued on the commit side only Any lock or unlock command issued on the transmit side will be ignored and the double transmit buffer lock error flag...

Page 1574: ...2n 1 EDS 1 Application triggers message buffer disable HL FR_MBCCSR 2n LCKT 1 FR_MBCCSR 2n LCKS 0 Application triggers message buffer lock HU FR_MBCCSR 2n LCKS 1 Application triggers message buffer un...

Page 1575: ...ration Control Status Registers FR_MBCCSRn The physical access to the message buffer data field is described in Section 33 6 3 1 Individual message buffers As indicated by Table 33 117 the application...

Page 1576: ...s to ensure that each committed message is transmitted at least once The CC will not start the Internal Message Transfer for a message buffer as long as the message data on the transmit side is not tr...

Page 1577: ...the application provides two messages and the first message is gets overwritten The message buffer does not match the next slot Figure 33 145 Internal message transfer in immediate commit mode 33 6 6...

Page 1578: ...t n considers only message buffers which are 1 enabled that is FR_MBCCSRn EDS 1 and 2 matches the next slot n that is FR_MBFIDRn FID n and 3 are the transmit side buffer in case of a double transmit m...

Page 1579: ...ffer assigned to a slot in the static segment though this buffer is added to the matching message buffers to indicate the slot assignment and to trigger the null frame transmission The cycle counter f...

Page 1580: ...sult is not defined in this case For more details see Section 33 7 6 Number of usable message buffers 33 6 8 Individual message buffer reconfiguration The initial configuration of each individual mess...

Page 1581: ...two single message buffers must have consecutive message buffer numbers and the smaller one must be even Message Buffers can be RC3 reconfigured if they are in the HDis state Figure 33 147 Message bu...

Page 1582: ...tion 33 6 4 FlexRay memory area layout 2 The second step is the programming of the configuration data register while the PE is in POC config The following steps configure the layout of the FIFO Config...

Page 1583: ...ted If the periodic timer expires and FIFOA FIFOB is not empty that is FLA 0 FLB 0 then the FIFO almost full interrupt flag FR_GIFER FAFAIF FR_GIFER FAFBIF is asserted 33 6 9 6 FIFO overflow error gen...

Page 1584: ...R_RFSIR automatically 33 6 9 8 1 FIFO interrupt flag update Th FIFO Interrupt Flag Update mode is configured when the FIFO update mode flag FR_MCR FUM is set to 0 In this mode FIFOA FIFOB will be upda...

Page 1585: ...ue Frame ID Append to FIFO vRF Frame ID No Frame Received FIFO full Set FIFO Overflow Interrupt Flag Message Buffer Found No Passed Passed Passed Yes vRF Header NFIndicator 0 Mask Rejection Filter Ran...

Page 1586: ...Frame ID Value Mask Rejection Filter can be configured to reject all frames by the following settings FR_RFFIDRFMR FIDRFMSK 0x000 Using the settings above Equation 33 13 can never be fulfilled 0 0 an...

Page 1587: ...R_RFMIDAFMR This filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit PPI set to 1 All other frames will pass this filter A received valid frame...

Page 1588: ...l channel A and the FlexRay Port A is used Depending on the setting of FR_MCR CHA and FR_MCR CHB the internal channel A behaves either as a FlexRay Channel A or FlexRay Channel B The bit FR_MCR CHA mu...

Page 1589: ...fields in the Protocol Operation Control Register FR_POCR The PE applies the external correction values in the next even odd cycle pair as shown in Figure 33 152 and Figure 33 153 CHI PE cfg A reg A...

Page 1590: ...of cycle 2n 1 If this field is written to after the end of the static segment of cycle 2n 1 it is not guaranteed that the external correction value is applied in cycle pair 2n 2 2n 3 If the value is n...

Page 1591: ...Frame ID ChA 1 Sync Frame ID ChA 2 Sync Frame ID ChA 3 Sync Frame ID ChA 4 Sync Frame ID ChA 5 Sync Frame ID ChA 6 Sync Frame ID ChA 7 Sync Frame ID ChA 8 Sync Frame ID ChA 9 Sync Frame ID ChA 10 Syn...

Page 1592: ...SR EVAL and the Even Cycle Table Written Interrupt Flag EVT_IF in the Protocol Interrupt Flag Register 1 FR_PIFR1 If the interrupt enable flag EVT_IE is set an interrupt request is generated To read t...

Page 1593: ...ol Status Register FR_SFTCCSR If the affected table is not currently written to the FlexRay memory area the lock is granted immediately and the lock status bit ELKS OLKS is set If the affected table i...

Page 1594: ...key slot is assigned 33 6 14 2 Key slot transmission in POC startup If a key slot is assigned and the CC is in the POC startup state startup null frames will be transmitted as specified by FlexRay Com...

Page 1595: ...n the Sync Frame ID Acceptance Filter Mask Register FR_SFIDAFMR A received synchronization frame with the frame ID FID passes the sync frame acceptance filter if Equation 33 23 or Equation 33 24evalua...

Page 1596: ...updates SEL field only 2 Read STBCSR The SEL field provides N and the ENB and STBPSEL fields provides the settings for signal N 33 6 16 2 Strobe signal timing This section provides detailed timing inf...

Page 1597: ...Register 0 FR_PIER0 is asserted an interrupt request is generated The status bit T1ST is set when the timer is triggered and is cleared when the timer expires and is non repetitive If the timer expire...

Page 1598: ...t the next macrotick start 33 6 18 Slot status monitoring The CC provides several means for slot status monitoring All slot status monitors use the same slot status vector provided by the PE The PE pr...

Page 1599: ...while transmission starts for slots in which the module does not transmit vSS TxConflict reception ongoing while transmission starts first valid channel that has received the first valid frame Receiv...

Page 1600: ...atus counter is incremented if its increment condition defined by the Slot Status Counter Condition Register FR_SSCCR matches the status vector provided by the PE All static slots the symbol window an...

Page 1601: ...Y 0 the internal slot status counter FR_SSCRn_INT is reset at each cycle start If the slot status counter is in the multicycle mode that is FR_SSCCRn MCY 1 the counter is not reset and incremented unt...

Page 1602: ...e CC will continue its operation after the occurrence of the system bus access failure but will not generate any system bus accesses until the start of the next communication cycle Since no data are r...

Page 1603: ...ted to the wakeup The CC sets the Wakeup Interrupt Flag FR_GIFER WUPIF when it has received a wakeup symbol on the FlexRay bus The CC generates an interrupt request if the interrupt enable bit FR_GIFE...

Page 1604: ...rrupt The Protocol Interrupt request is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit FR_GIFER PRIE is set 33 6 2...

Page 1605: ...pt FR_GIFER RBIE FR_MBCCSRn MTD RXBUF TXBUF FR_GIFER PRIE FR_GIFER WUPIE FR_MBCCSRn MBIE FR_PIER0 15 0 FR_PIER1 9 0 OR FR_GIFER CHIE n OR Transmit Message Buffer Interrupt FR_GIFER TBIE n OR OR FR_GIF...

Page 1606: ...nals FR_EEIFER FR_EEIFER LRNE_IE FR_EEIFER LRCE_IF FR_EEIFER LRCE_IE FR_EEIFER DRNE_IF FR_EEIFER DRNE_IE FR_EEIFER DRCE_IF FR_EEIFER DRCE_IE DRAM ECC LRAM Corrected Error Interrupt DRAM Non Corrected...

Page 1607: ...ay Communications System Protocol Specification Version 2 1 Rev A 33 6 22 PE data memory PE DRAM The PE Data Memory PE DRAM is 128 word 16 bit wide memory with byte access which contains the program d...

Page 1608: ...causes an response delay with a maximum of 1000 PE clock cycle 25 s If the conditions given in Section 33 6 22 3 PE DRAM write access limitations are fulfilled the data provided in PE DRAM Data Regis...

Page 1609: ...module on the occurrence and how the application can inject memory errors in order to trigger the report and response behavior 33 6 24 1 Memory error types A memory error is the distortion of one or m...

Page 1610: ...ported and the error overflow flag will be set to 1 If a memory error is detected for at least two banks of one memory the related error overflow flag is set to 1 to indicate a loss of error condition...

Page 1611: ...f the syndrome reported in ECC Error Report Code Register FR_EERCR for PE DRAM memory errors is shown in Table 33 132 Table 33 131 PE DRAM checkbits coding CODE CODE DATA 3 2 1 0 7 6 5 4 3 2 1 0 41 1...

Page 1612: ...All Zero Code Word If data 0 Corrected Error Parity Bit 4 0x0 0x1 Corrected Error Parity Bit 0 0x0 0x2 Corrected Error Parity Bit 1 0x0 0x3 Corrected Error Data Bit 0 0x0 0x4 Corrected Error Parity B...

Page 1613: ...uffer is not changed If the affected message buffer is a tx message buffer no frame will be transmitted from this message buffer in the next slot If the affected message buffer is a rx message buffer...

Page 1614: ...it EIE in the ECC Error Report and Injection Control Register FR_EERICR are set The error injection mode is configured by the EIM configuration bit in the ECC Error Report and Injection Control Regist...

Page 1615: ...he PE DRAM This sequence includes the setup of error injector followed by an application triggered write access to provoke an distortion of the memory content When the FlexRay module is in POC default...

Page 1616: ...Access Time Out Register FR_SYMATOR and the CHI clock frequency fCHI in MHz fulfill Equation 33 291 Eqn 33 29 If the SYMATOR TIMEOUT value and fCHI violates Equation 33 29 the behavior of the CC beco...

Page 1617: ...related initialization steps after a system reset 1 Configure CC a configure the control bits in the Module Configuration Register FR_MCR b configure the system memory base address in System Memory B...

Page 1618: ...nsition from POC default config into POC config 33 7 3 CHI LRAM error injection out of POC default config When the FlexRay module is out of the POC default config state it reads the configuration data...

Page 1619: ...est FlexRay slot is an corrected empty dynamic slot An corrected empty dynamic slot is a minislot and consists of gdMinislot corrected macroticks with a duration of gdMacrotick The minimum duration of...

Page 1620: ...mand is not queued and is lost If the command execution block of the PE is idle it selects the next accepted protocol command with the highest priority from the current protocol command vector accordi...

Page 1621: ...buffer has the message buffer number t and is configured as shown in Table 33 138 ALL_SLOTS 4 FREEZE READY CONFIG_COMPLETE fatal protocol error FREEZE READY CONFIG_COMPLETE fatal protocol error ALLOW...

Page 1622: ...a slot occurs if the slot is assigned to a node on a channel that node must transmit either a normal frame or a null frame on that channel Specifically a null frame will be sent if there is no data r...

Page 1623: ...he receive buffer will be found and the node can receive data and b for the cycles in the set 4n 2 which is assigned to the receive buffer only the receive buffer will be found and the node can receiv...

Page 1624: ...FlexRay Communication Controller FlexRay MPC5644A Microcontroller Reference Manual Rev 6 1624 Freescale Semiconductor...

Page 1625: ...PIT RTI 32 bit counter 4 Timer Channels 1 Real Time Interrupt RTI timer channel clocked from the crystal oscillator that can be used to wake the part from stop mode The counter period of a running ti...

Page 1626: ...nterrupts and trigger DMA channels Real Time Interrupt Timer RTI is a dedicated interrupt timer which runs on a separate clock and can be used for system wakeup 34 2 2 Features The main features of th...

Page 1627: ...effect 34 4 2 Register descriptions This section describes in address order all the PIT registers and their individual bits Table 34 1 PIT memory map Address offset Use Access Location 0x000 PIT Modu...

Page 1628: ...0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIS _RTI MDIS FRZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figu...

Page 1629: ...ount down until it reaches 0 then it will generate an interrupt and load this register value again Writing a new value to this register will not restart the timer instead the value will be loaded once...

Page 1630: ...r see Figure 34 2 Offset channel_base 0x08 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24...

Page 1631: ...the previous one is cleared Since in the case of the RTI clearing the interrupt crosses clock domains a minimum load value of 32 should be maintained If desired the current counter value of the timer...

Page 1632: ...t allowing the developer to halt the processor investigate the current state of the system e g the timer values and then continue the operation 34 5 2 Interrupts All of the timers support interrupt ge...

Page 1633: ...20 ns and the 10 MHz frequency equates to a clock period of 100 ns Therefore the RTI timer needs to trigger every 500 ms 100 ns 5000000 cycles Timer 1 needs to trigger every 5 12 ms 20 ns 256000 cycl...

Page 1634: ...rrupt Timer PIT MPC5644A Microcontroller Reference Manual Rev 6 1634 Freescale Semiconductor PIT_TCTRL1 TEN start timer 1 Timer 3 PIT_LDVAL3 0x0016E35F setup timer 3for 1500000 cycles PIT_TCTRL3 TEN s...

Page 1635: ...es See Chapter 5 Operating Modes and Clocking for details The power management controller contains circuitry to generate the internal 3 3 V supply and to control the regulation of 1 2 V supply with ex...

Page 1636: ...R vddreg VBGref LVI3p3ref LVI1p2ref LVI1p0ref REG3p3ref REG1p2ref LVI VREG Reference LVI5 vddreg LVI3 vddeh LVI3 vdd33 LVI1 2 vdd LVI1 0 vdd POR5 vddreg POR3 vddeh POR3 vdd33 POR1 2 vdd Vreg1p2 Vreg3p...

Page 1637: ...tors are used For external power supply requirements check the PMC electrical specifications in the PMC Operating Conditions and External Regulators Voltage table in the device data sheet 2 Within the...

Page 1638: ...to an external 3 3 V supply 35 2 1 4 VDD This is the 1 2 V supply coming from the emitter of an external NPN ballast transistor whose base current is supplied by VRCCTL If the internal voltage regulat...

Page 1639: ...the device See Section 4 5 Reset source descriptions for more details After a software system reset different status flags are set in the SIU_RSR register NOTE LVI resets and interrupts are only enab...

Page 1640: ...uses system reset 4 LVREC 1 2 V LVI reset enable This bit defines whether an LVI assertion on the 1 2 V supply will generate system reset or not 0 No reset LVI assertion on the 1 2 V supply does not c...

Page 1641: ...power supply goes below the corresponding LVI threshold The LVI interrupt is independent from LVI reset If both interrupt and reset are enabled then reset and interrupt will be generated but reset wi...

Page 1642: ...Nominal configuration 0111 4 43 V 0110 4 41 V 0101 4 39 V 0100 4 37 V 0011 4 35 V 0010 4 33 V 0001 4 31 V 0000 4 29 V Default 1111 4 27 V 1110 4 25 V 1101 4 23 V 1100 4 21 V 1011 4 19 V 1010 4 17 V 1...

Page 1643: ...V Default 1111 3 07 V 1110 3 05 V 1101 3 03 V 1100 3 01 V 1011 2 99 V 1010 2 97 V 1001 2 95 V 1000 2 93 V Note The recommended value for the LVD33TRIM is 0b0011 In the cut 1 device the register should...

Page 1644: ...2 V 0010 1 20 V 0001 1 18 V 0000 1 16 V Default 1111 1 14 V 1110 1 12 V 1101 1 10 V 1100 1 08 V 1011 1 06 V 1010 1 04 V 1001 1 02 V 1000 1 0 V Offset PMC_BASE 0x0008 Access User read write 0 1 2 3 4 5...

Page 1645: ...this bit always returns 0 0 No effect 1 Clears LVFVSTBY 14 Reserved 15 V33DIS 3 3 V Internal Regulator Shutdown status bit 0 Enabled Vreg3p3 ON 1 Disabled Vreg3p3 OFF 16 LVFCR Reset pin supply VDDEH6...

Page 1646: ...on the VDDEH1 supply 26 LVF50 5 V LVI flag This read only bit is the LVI interrupt flag associated with the 5 V supply of the voltage regulator It can be cleared by the CPU by writing 1 to the LVFC50...

Page 1647: ...NVUSRO register Non Volatile User Option register in the flash memory See Section 35 4 3 3 3 V internal voltage regulator for more details In this case there is no need of external LVI monitoring As P...

Page 1648: ...r is 0000 corresponding to the rising trip point voltage of 4 29 V This is the typical default value the real default value may vary from sample to sample according to process temperature and voltage...

Page 1649: ...voltage may be read Moreover if an external 3 3 V voltage source will be used the user can disable this regulator by clearing the shutdown bit NVUSRO V33DIS The user might have both internal 3 3 V re...

Page 1650: ...according to process temperature and voltage supply conditions as detailed in the PMC Electrical Characteristics table in the device data sheet The LVIs can be programmed to trigger power on reset en...

Page 1651: ...e adjustable via software by writing to field PCM_TRIMR LVDCTRIM which selects one of the 16 voltages available The reset value of the 4 bit register is 0000 corresponding to a rising trip point volta...

Page 1652: ...e monitored respectively by the LVI 1 2 V and LVI 3 3 V circuits for this purpose Figure 35 8 POR rising and falling edges Figure 35 9 POR LVI relative rising and falling edges POR indeterminate POR_B...

Page 1653: ...ains other than the system clock A synchronized and filtered assertion of the RESET pin will hold the device in system reset The synchronizers and filter are reset with POR so that RESET appears to be...

Page 1654: ...row Note the field LVD33TRIM of the register TRIMR must be programmed with 0011 at least in order to enhance the LVI33 threshold by 60 mV and monitor the VDD33 Voltage in all the corners voltage proc...

Page 1655: ...ence is monitored or not by the Clock Quality Monitor If the reference is the crystal oscillator it is monitored If the reference is an external clock it is not monitored The PLLREF value during POR i...

Page 1656: ...al PMC signals eQADC channel ADC Description 45 ADC0 ADC1 Buffered Band Gap 128 ADC0 ADC1 Temp Sensor 129 ADC0 ADC1 VSSA 144 ADC0 Buffered Band Gap 145 ADC0 Reference Voltage for 1 2 V LVD 146 ADC0 Re...

Page 1657: ...n 36 5 4 JTAGC block instructions available on this device Table 36 1 Device specific parameters Parameter Value Number of JCOMP bits used 1 Length of the boundary scan chain path for the device 248 N...

Page 1658: ...n technique as defined in the IEEE 1149 1 2001 standard All data input to and output from the JTAGC block is communicated in serial format 36 2 2 Features The JTAGC block is compliant with the IEEE 11...

Page 1659: ...hronous entry into the reset state While in reset the following actions occur The TAP controller is forced into the Test Logic Reset state thereby disabling the test logic and allowing normal operatio...

Page 1660: ...l output for test instructions and data TDO is three stateable and is actively driven only in the Shift IR and Shift DR states of the TAP controller state machine which is described in Section 36 5 3...

Page 1661: ...t data register to be accessed or both Instructions are shifted in through TDI while the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latch...

Page 1662: ...d to the manufacturer by the JEDEC The shift register LSB is forced to logic 1 on the rising edge of TCK following entry into the Capture DR state Therefore the first bit to be shifted out after selec...

Page 1663: ...ut pin data force fixed values on output pins and select a logic value and direction for bidirectional pins Each bit of the boundary scan register represents a separate boundary scan register cell as...

Page 1664: ...For more detail on TAP sharing via JTAGC instructions refer to Section 36 5 4 7 ACCESS_AUX_TAP_x instructions Data is shifted between TDI and TDO through the selected register starting with the least...

Page 1665: ...LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1...

Page 1666: ...36 5 4 JTAGC block instructions The JTAGC block implements the IEEE 1149 1 2001 defined instructions listed in Table 36 7 This section gives an overview of each instruction refer to the IEEE 1149 1 2...

Page 1667: ...s transferred to the parallel outputs of the boundary scan register cells on the falling edge of TCK in the Update DR state The data is applied to the external output pins by the EXTEST or CLAMP instr...

Page 1668: ...JTAG pins are transferred to the selected TAP controller Any data input via TDI and TMS is passed to the selected TAP controller and any TDO output from the selected TAP controller is sent back to the...

Page 1669: ...ss of data However the system clock is not synchronized to TCK internally Any mixed operation using both the test logic and the system functional logic requires external synchronization To initialize...

Page 1670: ...JTAG Controller JTAGC MPC5644A Microcontroller Reference Manual Rev 6 1670 Freescale Semiconductor...

Page 1671: ...ram Trace via Branch Trace Messaging BTM Branch trace messaging displays program flow discontinuities direct branches indirect branches exceptions etc allowing the development tool to interpolate what...

Page 1672: ...s control bit still needs to be programmed when the device is assembled in any other package Table 37 1 shows the maximum trace port frequencies supported in different configurations as well as the op...

Page 1673: ...or the design center responsible for the design of the device TECD 0x2B Part Identification Number npc_did_pn_plug 9 0 Part number of the device 0x202 Part Revision Number npc_did_rev_plug 3 0 Revisio...

Page 1674: ...l development interface blocks to share the port and appear to the development tool to be a single block 37 2 2 Features The NPC block performs the following functions Controls arbitration for ownersh...

Page 1675: ...et While in reset the following actions occur The TAP controller is forced into the Test Logic Reset state The auxiliary output port pins are negated The TDI TMS and TCK TAP inputs are ignored when in...

Page 1676: ...atus indication The EVTO output of the NPC is generated based on the values of the individual EVTO signals from all Nexus blocks that implement the signal 37 3 2 2 JCOMP JTAG Compliancy The JCOMP sign...

Page 1677: ...2 7 TDO Nexus Test Data Output Test Data Output TDO pin transmits serial output for instructions and data TDO is three stateable and is actively driven in the SHIFT IR and SHIFT DR controller states T...

Page 1678: ...shifted in through TDI while the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the Update...

Page 1679: ...er These bits contain the revision number of the part 27 2 2 DC Design Center These bits indicate the device design center 21 1 2 PIN Part Identification Number These bits contain the part number of t...

Page 1680: ...messages 0 A subset of MDO pins are used to transmit messages 30 MCKO_GT MCKO Clock Gating Control This bit is used to enable or disable MCKO clock gating If clock gating is enabled the MCKO clock is...

Page 1681: ...de entry acknowledged 7 1 Reserved 0 PSTAT_EN Processor Status Mode Enable1 This bit enables processor status PSTAT mode In PSTAT mode all auxiliary output port MDO pins are used to transmit processor...

Page 1682: ...ort is shared by each of the Nexus modules on the device The NPC communicates with each of the Nexus modules and arbitrates for access to the port 37 5 2 1 Output message protocol The protocol for tra...

Page 1683: ...e device ID register and the port replacement output message on the MDO pins The device ID message can also be sent out serially through TDO Table 37 9 describes the device ID and port replacement out...

Page 1684: ...h field is sized such that it does not end on a port boundary it is necessary to extend and zero fill the remaining bits after the highest order bit so that it can end on a port boundary Multiple fixe...

Page 1685: ...the IEEE 1149 1 2001 state machine shown in Figure 37 9 The Nexus controller state machine is defined by the IEEE ISTO 5001 2010 standard It is shown in Figure 37 10 The instructions implemented by th...

Page 1686: ...ssertion of the power on reset signal or setting JCOMP to a value other than the NPC enable encoding resets the NPC TAP controller When not in power on reset the NPC TAP controller is enabled by drivi...

Page 1687: ...OGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1...

Page 1688: ...EXUS ENABLE instruction This instruction is shifted in via the SELECT IR SCAN path and loaded in the UPDATE IR state At this point the Nexus controller state machine shown in Figure 37 10 transitions...

Page 1689: ...from the IEEE 1149 1 2001 shifter to the register during the UPDATE DR state When reading a register there is no requirement to shift out the entire register contents Shifting may be terminated once...

Page 1690: ...is enabled but not transmitting messages The setting of the MCKO_GT bit inside the PCR determines whether or not MCKO gating control is active The MCKO_GT bit resets to a logic 0 In this state gating...

Page 1691: ...DO 0 driven high 37 6 Initialization Application information 37 6 1 Accessing NPC tool mapped registers To initialize the TAP for Nexus register accesses the following sequence is required 1 Enable th...

Page 1692: ...Nexus Port Controller NPC MPC5644A Microcontroller Reference Manual Rev 6 1692 Freescale Semiconductor...

Page 1693: ...up to 32 signals from the application software In an application each bit is generally associated with a specific data set Only the processor core and DMA module can set bits in this register The bits...

Page 1694: ...or access to the registers The PBRIDGE is connected to a slave port of the Crossbar bus interface XBAR Connected to the XBAR master ports are the core e200z4 with one master port for the Instruction a...

Page 1695: ...isters is controlled based on the XBAR Master ID of the accessing module The table below shows the XBAR Master IDs for each of port 1 DTS_SEMAPHORE bits are cleared automatically when read through the...

Page 1696: ...e 32 bit registers are implemented The rest of the memory map 0xC3F9_C00C through 0xC3F9_FFFF is reserved 38 5 Register descriptions 38 5 1 DTS Output Enable Register DTS_ENABLE This DTS_ENABLE regist...

Page 1697: ...0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTS_EN W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplement...

Page 1698: ...11 12 13 14 15 R AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R AD15 AD14 AD1...

Page 1699: ...e register Nexus can only read this register but all bits are cleared after the read operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19...

Page 1700: ...o the DTS_STARTUP register 3 The CPU user application software then reads the value of the DTS_STARTUP register Based on this value different initialization options can be selected The bits can be use...

Page 1701: ...Development Trigger Semaphore DTS MPC5644A Microcontroller Reference Manual Rev 6 Freescale Semiconductor 1701...

Page 1702: ...Development Trigger Semaphore DTS MPC5644A Microcontroller Reference Manual Rev 6 1702 Freescale Semiconductor...

Page 1703: ...shadow Row FL_1 address range changed Chapter 3 Signal Description Signal Properties table Removed Signal column Added Function column containing description of all Pins Removed Default State After R...

Page 1704: ...ister renamed to SLMLR LMS register renamed to LMSR HBS register renamed to HSR ADR register renamed to AR PFCR1 register renamed to BIUCR PFAPR register renamed to BIUAPR PFCR2 register renamed to BI...

Page 1705: ...tchdog Timer SWT SWT_CR register renamed to SWT_MCR Chapter 20 Boot Assist Module BAM Calibration boot is not supported EBI boot is supported instead Chapter 21 Configurable Enhanced Modular IO Subsys...

Page 1706: ...renamed to DSPI_RSER TFFFRE DSPI_RSER TFFF_DIRS renamed to DSPI_RSER TFFFDIRS DSPI_RSER DPEF_RE renamed to DSPI_RSER DPEFRE DSPI_RSER SPEF_RE renamed to DSPI_RSER SPEFRE DSPI_RSER DDIF_RE renamed to...

Page 1707: ...Fields formerly found in registers SCISR1 SCIRSR2 LINSTAT1 and LINSTAT2 are now contained in SCI_SR Fields formerly found in registers LINCTRL1 LINCTRL2 and LINCTRL3 are now contained in SCI_LCR The L...

Page 1708: ...C renamed to MCR MBFEN CR register fields renamed CR BOFF_MSK renamed to CR BOFFMSK CR ERR_MSK renamed to CR ERRMSK CR CLK_SRC renamed to CR CLKSRC CR TWRN_MSK renamed to CR TWRNMSK CR RWRN_MSK rename...

Page 1709: ...load is lower it is possible to reduce the requirements of the bypass capacitor to 1 F 5 F and 100 m ESR MCR register reset value is 0x98000000 was 0x00000000 SR register reset value is 0x03000000 or...

Page 1710: ...tion following text deleted Tolerance of the 3 3 V supply is 5 10 including line and load variation Detail on disabling voltage regulator added In 3 3V LVI section noted that there are 2 LV monitors A...

Page 1711: ...list Core clock speed for device is 150 MHz was 145 MHz Correction there are 6 reaction channels noted as 5 Development Trigger Semaphore DTS added to features list and feature details FlexRay now has...

Page 1712: ...ll on previous devices ANZ function added to pin AN11 Reaction channels added to eTPU2 RCH0_A A3 added to ETPU_A 14 PCR 128 RCH0_B A2 added to ETPU_A 20 PCR 134 RCH0_C A2 added to ETPU_A 21 PCR 135 RC...

Page 1713: ...Clocking Max clock speed is now 150 MHz was 145 MHz EPREDIV IDF divider 7 for 150 MHz clock was 8 for 145 MHz clock EMFD NDIV loop divider 60 for 150 MHz clock was 58 for 145 MHz clock VCO clock out...

Page 1714: ...orm Peripheral Access Control Registers OPACR Chapter 11 Flash memory Added UTn registers to memory map MCR field description Removed references to Tdone and Tres from DONE field description Removed r...

Page 1715: ..._CSR DPEF DSPI_CSR DDIF DSPI_DSR SPEF DSPI_DSR DPEF DSPI_DSR DDIF GIFER LRNE GIFER DRNE GIFER LRCE GIFER DRCE REACM_GE REACM 0 REACM 1 REACM 2 REACM 3 Other updates Interrupt 307 source updated Larges...

Page 1716: ...es to SIU_PCR126 New function added RCH4_C PA field expanded to 3 bits Changes to SIU_PCR128 New function added RCH0_A PA field expanded to 4 bits Changes to SIU_PCR129 New function added RCH1_A PA fi...

Page 1717: ...RCH3_C PA field expanded to 3 bits Changes to SIU_PCR219 This pin is not used to select GPIO 219 Instead it is used to control the electrical characteristics of the MCKO pin New SIU_PCR registers add...

Page 1718: ...ter descriptions Changed signal name notation for DSPI PCSxn or DSPI_x_CS n is now DSPI_x_PCS n SOUTx is now DSPI_x_SOUT SINx is now DSPI_x_SIN SCKx is now DSPI_x_SCK SIU address map Added page index...

Page 1719: ...PCR 68 69 Added new section Enabling Debug of a Censored Device Chapter 23 Enhanced Time Processing Unit eTPU2 Changes to register reset values ETPU_TBCR register reset value is 0x2000_0000 ETPU_REDCR...

Page 1720: ...or Detection Module now has 128 message buffers was 64 New sections added Controller Host Interface Clocking System Bus Access PE Data Memory PE DRAM CHI Lookup Table Memory CHI LRAM Memory Content Er...

Page 1721: ...Architecture Editorial and formatting changes Chapter 1 Introduction Nexus development interface NDI is compliantIEEE ISTO 5001 2003 and 2010 standards Updates to device comparison table Interrupt con...

Page 1722: ...ns See SIU_PCR219 section in SIU chapter for details Clarification Following signals are active low EBI CS 0 3 EBI BDIP EBI OE EBI TA EBI TS EBI RD_WR EBI WE 0 1 BE 0 1 Nexus MSEO 0 1 Nexus RDY IRQ 0...

Page 1723: ...eDMA Notation change Register bitfield naming changed from MODULE_REGISTER FIELD to MODULE_REGISTER FIELD Chapter 10 Peripheral Bridge PBRIDGE Renamed Master Privilege Register MPROT to Master Privil...

Page 1724: ...is PCR is unusual in that it controls configuration for two pins GPIO 219 and MCKO but not all fields apply to both pins SIU_SYSDIV field description Added note to SYSCLKDIV field description to expla...

Page 1725: ...ow chart updated Chapter 22 Configurable Enhanced Modular IO Subsystem eMIOS200 Added Device specific features section includes notation that Doze mode is not supported STAC client submodule section R...

Page 1726: ...the new DOFF value is immediately used in the channel output Changes to REACM_STBK register Note added to SHARED_TIMER field When using the shared timer for sequence advance the counted time consider...

Page 1727: ...ture Chapter 1 Introduction Conditionalized note 6 of table Andorra 4M device comparison as FSL_Specific Added a column for Andorra2M features and hence changed title of table1 and section 1 2 to MPC5...

Page 1728: ...slot assignment Chapter 23 Enhanced Time Processing Unit eTPU2 Removed Register ETPUWDSR Chapter 25 Enhanced Queued Analog to Digital Converter EQADC In the figure On Chip ADC Control Scheme renamed b...

Page 1729: ...RTI is a dedicated interrupt timer Chapter 34 FlexRay Communication Controller FlexRay Updated Table 834 Channel assignment description Previous errata err002423 e6858715PDM integrated into the refer...

Page 1730: ...om BOOTCFG 0 Down to Down in row BOOTCFG 1 column Status During Reset changed the value from Down to BOOTCFG 1 Down and column Status After Reset changed from BOOTCFG 1 Down to Down in row WKPCFG colu...

Page 1731: ...o No request Changed Source and Description from Reserved to Updated Section 8 5 8 Dynamic programming Multi Layer AHB Crossbar Switch In Figure 9 4 Slave General Purpose Control Register XBAR_SGPCRn...

Page 1732: ...rom The IMUX Select Register 10 SIU_ISEL10 or SIU_DECFIL1 register contains bit fields that specifywhich eTPU output is used to trigger the decimation filter result output buffer for decimation filter...

Page 1733: ...SPI DSI Parallel Input Select Register 1 DPSI_PISR1 DSPI DSI Parallel Input Select Register 2 DPSI_PISR2 DSPI DSI Parallel Input Select Register 3 DPSI_PISR3 DSPI DSI Deserialized Data Interrupt Mask...

Page 1734: ...ler In Table 37 1 Nexus trace port routing and speed row Debug Cal package changes done are as follows In column Port routing bit NPC_PCR NEXCFG changed the value to Don t care In column CAL_MDO 4 11...

Page 1735: ...he application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provide...

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