NXP Semiconductors MPC5644A, Reference Manual, Page: 565 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 565
Offset 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
PREDIV MFD
0
RFD
LOC
EN
LOL
RE
LOC
RE
W
Reset 0 –
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
0 –
1
–
1
–
1
0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
LOL
IRQ
LOC
IRQ
0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 Reset value is determined by the SoC integration.
Figure 17-2. Synthesizer Control Register (SYNCR)
Table 17-6. SYNCR field descriptions
Field Description
0 Reserved, should be cleared.
1–3
PREDIV
Predivider
This 3-bit field controls the value of the divider on the input clock. The output of the predivider circuit
generates the reference clock to the FMPLL analog loop. The value 111 causes the input clock to be
inhibited.
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Clock inhibit
4–8
MFD
Multiplication factor divider
This 5-bit field controls the value of the divider in the FMPLL feedback loop. The value specified by the
MFD bits establishes the multiplication factor applied to the reference frequency.
000xx Invalid
00100 Divide by 8
00101 Divide by 9
00110 Divide by 10
...
10011 Divide by 23
10100 Divide by 24
10101 Invalid
1011x Invalid
11xxx Invalid
9 Reserved, should be cleared.