NXP Semiconductors MPC5644A, Reference Manual, Page: 759 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 759
• Immediately force a logic level.
The output signal may also be forced to a logic level, independently of the output value from the channel
logic, by one of the four (each engine) output disable input signals ipp_ind_etpuodis (see
Section 24.3.2.4,
ipp_ind_etpu_odis_[1|2]([0 – 3]) eTPU Channel Output Disable Signals ).
The output signal driver may be, depending on MCU integration, enabled by the output buffer enable
internal signal that comes from eTPU. In this case, the output buffer can be controlled by microcode,
through a specific microinstruction field. There is one independent output buffer Enable signal for each
channel. For more information on output control from microcode, refer to
Section 24.5.9.3.3, Transition
detection and pin action control .
24.3.2.2 ipp_ind_etpuch_[1|2]([0 – 31]) — eTPU Channel Input Signals
Each channel input signal is associated with a channel. The microcode can directly control the effect of the
transition edge. Each channel can be programmed to sense a transition when a rising and/or falling edge
is detected. The channel logic can also process two transition events, and relate these events to each other
and to other programmed timer events. The edge sensitivities of the two transition events are configured
independently by microcode. For further information refer to
Section 24.5.5, Enhanced Channels , and
Section 24.5.9.3.3, Transition detection and pin action control .
Each channel input signal has an associated synchronizer made of two flip-flops sampling the signal on
every other system clock
1
, followed by a digital filter. This digital filter can work in three submodes,
whose purpose is to filter out noise pulses that have width less then a programmed value of system clocks,
preventing these transitions from being input to the transition detect logic. The synchronizer and digital
filter are guaranteed to pass pulses that are greater than a programmed value. All channel input filters in
one engine work on the same mode and sampling clock. For more information on channel input filters,
refer to
Section 24.5.5.6, Enhanced Digital Filter – EDF . In one of the Angle Modes, the output of the
digital filter of channel 0 is replaced by the output of TCRCLK digital filter (see Section 24.5.7, EAC –
eTPU angle counter ).
24.3.2.3 ipp_ind_tcrclk_etpu_[1|2] — Time Base Clock Signal — TCRCLK
TCRCLK is an input signal used to control the Time Bases TCR1 and TCR2. There is one independent
TCRCLK input for each engine. For pulse accumulator operations TCRCLK can be used as a gate for a
counter based on the system clock divided by eight. For Angle operations TCRCLK can be used to get the
tooth transition indications in Angle Mode. Further details can be found on
Section 24.5.6, Time Bases ,
and Section 24.5.7, EAC – eTPU angle counter .
Like the channel input signals, the TCRCLK signal has an associated synchronizer followed by a digital
filter. This digital filter can work in two submodes, whose purpose is to filter out noise pulses that have
width less then a programmed value of system clocks, preventing these transitions from being input to the
transition detect logic. The synchronizer and digital filter are guaranteed to pass pulses that are greater than
1. Note that the minimum pulse width is one microcycle (two system clocks), and slow 5V pads may not be able to transfer it on
time. For generation of very short pulses the eTPU pads have to be programmed by the system integration for fast operation
mode with the voltage levels defined for fast pad operation in the MCU technology.
1. Sampled on the T4 microcycle phase, see
Section 24.7.1, Microcycle and I/O timing .