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Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
893
Figure 24-51. Time base synchronization
24.5.6.5
TCRCLK digital filter
The TCRCLK signal has an improved integrating digital filter with a 2-bit up-down counter. The counter
counts up to 3 when a high signal level is detected, or down to 0 when a low level is detected. The signal
state is updated to one when the counter stops at 3, or zero when the counter stops at 0. The field TCRCF
in register ETPU_TBCR (see
Section 24.4.3.1, ETPU_TBCR – eTPU Time Base Configuration Register
)
determines whether the TCRCLK signal input (after a synchronizer) is filtered with the same filter clock
as the channel input signals (see
Section 24.5.5.6, Enhanced Digital Filter – EDF
) or uses the system clock
divided by 2, and also whether the TCRCLK digital filter works in integrator mode or the same two sample
mode as the channel filters (see
The TCRCLK filter delay and prescaling determines the minimum detectable TCRCLK pulse widths and,
therefore, its maximum frequency, as shown in
Section 24.5.5.6.5, Filter Clock Prescaler
.
The TCRCLK signal delay from the module input to TCR1/TCR2 incrementing or detection in the EAC
logic is explained in
Section 24.7.1.2, Input/Output signal delays
24.5.7
EAC – eTPU angle counter
24.5.7.1
General
The EAC logic contains a mechanism which follows the flywheel angle, based on the tooth rate. This
hardware works in combination with the TCRCLK signal, the TCR2 counter and Channel 0, 1 or 2
(depending on the ETPU_TBCR field AM) to generate angle information on the TCR2 bus which is passed
to all the local engine channels. The EAC helps to implement a digital angle PLL (see
), which
eTPU SYSTEM
etpu_gtbe_out
etpu_gtbe_in
ETPU_MCR[GTBE]
eTPU SYSTEM
etpu_gtbe_out
etpu_gtbe_in
MODULE X
gtbe_out
gtbe_in
SYNCHRONIZATION
LOGIC
SYNCHRONIZATION
BETWEEN eTPU TIME
BASES ONLY
SYNCHRONIZATION BETWEEN eTPU TIME
BASES AND OTHER MODULE TIME BASES
ETPU_MCR[GTBE]
Summary of Contents for MPC5644A
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