NXP Semiconductors MPC5644A, Reference Manual, Page: 1678 / 1735

Nexus Port Controller (NPC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1678 Freescale Semiconductor
37.4.1 Register descriptions
This section consists of NPC register descriptions.
37.4.1.1 Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS instruction or any unimplemented instructions are active. After entry into the
Capture-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after
selecting the bypass register is always a logic 0.
37.4.1.2 Instruction Register
The NPC block uses a 4-bit instruction register as shown in Figure 37-2 . The instruction register is
accessed via the SELECT_IR_SCAN path of the tap controller state machine, and allows instructions to
be loaded into the block to enable the NPC for register access (NEXUS_ENABLE) or select the bypass
register as the shift path from TDI to TDO (BYPASS or unimplemented instructions).
Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state, and latched on the
falling edge of TCK in the Update-IR state. The latched instruction value can only be changed in the
Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the Test-Logic-Reset state
results in synchronous loading of the BYPASS instruction. Asynchronous entry into the Test-Logic-Reset
state results in asynchronous loading of the BYPASS instruction. During the Capture-IR TAP controller
state, the instruction register is loaded with the value of the previously executed instruction, making this
value the register’s read value when the TAP controller is sequenced into the Shift-IR state.
Figure 37-2. 4-bit Instruction Register
37.4.1.3 Nexus Device ID Register (DID)
The device identification register, shown in Figure 37-3 , allows the part revision number, design center,
part identification number, and manufacturer identity code of the part to be determined through the
auxiliary output port.
Table 37-4. NPC registers
Index Register
0 Device ID Register (DID)
127 Port Configuration Register (PCR)
3 2 1 0
R Previous Instruction Opcode
W Instruction Opcode
Reset: BYPASS Instruction Opcode (0xF)