FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1436
Freescale Semiconductor
The sensitivity to CAN bus activity can be modified by applying a low-pass filter function to the Rx CAN
input line while in Stop Mode. See the WAK_SRC bit in
Section 32.4.5.1, Module Configuration Register
. This feature can be used to protect FlexCAN from waking up due to short glitches on the CAN
bus lines. Such glitches can result from electromagnetic interference within noisy environments.
32.5.10 Interrupts
The module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts
due to Ored interrupts from message buffers, Bus Off, Error, Tx Warning, Rx Warning and Wake Up). The
number of actual sources depends on the configured number of Message Buffers.
Each one of the message buffers can be an interrupt source, if its corresponding bit in the IMRL or IMRH
register is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the
assumption that the buffer is initialized for either transmission or reception. Each of the buffers has
assigned a flag bit in the IFRL or IFRH register. The bit is set when the corresponding buffer completes a
successful transmission/reception and is cleared when the CPU writes it to ‘1’ (unless another interrupt is
generated at the same time).
NOTE
It must be guaranteed that the CPU only clears the bit causing the current
interrupt. For this reason, bit manipulation instructions (BSET) must not be
used to clear interrupt flags. These instructions may cause accidental
clearing of interrupt flags which are set after entering the current interrupt
service routine.
If the Rx FIFO is enabled (MCR[FEN] set), the interrupts corresponding to MBs 0 to 7 have a different
behavior. Bit 7 of the IFRL becomes the “FIFO Overflow” flag; bit 6 becomes the FIFO Warning flag, bit
5 becomes the “Frames Available in FIFO flag” and bits 4–0 are unused. See
for more information.
A combined interrupt for all message buffers is also generated by an Or of all the interrupt sources from
message buffers. This interrupt gets generated when any of the message buffers generates an interrupt. In
this case the CPU must read the IFRL or IFRH register to determine which message buffer caused the
interrupt.
The other five interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up) generate
interrupts like the message buffer ones, and can be read from the Error and Status Register. The Bus Off,
Table 32-22. Wake-up from Stop Mode
SLF_WAK
WAK_MSK
MCU clocks enabled
Wake-up interrupt
generated
0
0
No
No
0
1
No
No
1
0
No
No
1
1
Yes
Yes
Summary of Contents for MPC5644A
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