NXP Semiconductors MPC5644A, Reference Manual, Page: 592 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
592 Freescale Semiconductor
18.4.4.3 ECC Error Generation Register (ECSM_EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the ECSM_EEGR is associated with the RAM, similar capabilities exist for
the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is
supported for the same two reasons previously identified.
For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit non-correctable errors that are terminated with an error response.
Register address: ECSM Base + 0x004A (0xFFF4_004A)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FR
CAP
0
FRC
1
B
I
1
1
This field is writable only in test mode in cut 1.0 devices.
FR
1
1
BI
1
0 0
F
R
CN
CI
FR1N
CI
0 ERRBIT[6:0]
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented
Figure 18-6. ECC Error Generation Register (ECSM_EEGR)