NXP Semiconductors MPC5644A, Reference Manual, Page: 1498 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1498 Freescale Semiconductor
Table 33-53 . For a detailed description of slot status monitoring, refer to Section 33.6.18, Slot status
monitoring ”.
NOTE
Slot status information of the message buffers should not be used when any
one of the the error flags FR_CHIERFR[SBCF_EF] or
FR_CHIERFR[ILSA_EF] is set.
33.5.2.47 Slot Status Counter Condition Register (FR_SSCCR)
This register is used to access and program the four internal non-memory mapped Slot Status Counter
Condition Registers FR_SSCCR0 to FR_SSCCR3. Each of these four internal slot status counter condition
Table 33-52. FR_SSSR field description
Field Description
WMD Write Mode — This control bit defines the write mode of this register.
0 Write to all fields in this register on write access.
1 Write to SEL field only on write access.
SEL Selector — This field selects one of the four internal slot status selection registers for access.
00 select FR_SSSR0.
01 select FR_SSSR1.
10 select FR_SSSR2.
11 select FR_SSSR3.
SLOTNUMBER Slot Number — This field specifies the number of the slot whose status will be saved in the
corresponding slot status registers.
Note: If this value is set to 0, the related slot status register provides the status of the symbol
window after the NIT start, and provides the status of the NIT after the cycle start.
Table 33-53. Mapping between FR_SSSRn and FR_SSRn
Internal Slot
Status Selection
Register
Write the slot status of the slot selected by FR_SSSRn for each
Even communication cycle Odd communication cycle
For Channel B
to
For Channel A
to
For Channel B
to
For Channel A
to
FR_SSSR0 FR_SSR0[15:8] FR_SSR0[7:0] FR_SSR1[15:8] FR_SSR1[7:0]
FR_SSSR1 FR_SSR2[15:8] FR_SSR2[7:0] FR_SSR3[15:8] FR_SSR3[7:0]
FR_SSSR2 FR_SSR4[15:8] FR_SSR4[7:0] FR_SSR5[15:8] FR_SSR5[7:0]
FR_SSSR3 FR_SSR6[15:8] FR_SSR6[7:0] FR_SSR7[15:8] FR_SSR7[7:0]
Base + 0x0066 16-bit write access required Write: Anytime
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0
SEL
0
CNTCFG MCY VFR SYF NUF SUF STATUSMASK[3:0]
W WMD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-47. Slot Status Counter Condition Register (FR_SSCCR)