NXP Semiconductors MPC5644A, Reference Manual, Page: 477 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 477
16.6.15.92 Pad Configuration Register 139 (SIU_PCR139)
Figure 16-125. Pad Configuration Register (SIU_PCR139)
16.6.15.93 Pad Configuration Register 140 (SIU_PCR140)
Figure 16-126. Pad Configuration Register (SIU_PCR140)
S0x156
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 PA OBE
1
1
When configured as IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPU_A[25] and
GPIO[139] when configured as outputs.
IBE
2
2
When configured as IRQ, DSPI_C_S or GPO, the IBE bit may be set to one to reflect the pin state in
the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. The IBE bit must be set
to one for both ETPU_A[25] and GPIO[139] when configured as inputs.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[25] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved
Table 16-128. SIU_PCR139 PA values
Signal Name Module Description I/O
1,2
1
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE
bits. Set IBE = 1 for input or OBE = 1 for output.
2
For I/O functions that change direction dynamically, such as the external data bus, switching between input and
output is handled internally and the IBE and OBE bits are ignored.
PA value
Primary ETPU_A[25]
3
3
The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings.
Please see
Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) , for more detail.
eTPU eTPU channel I/O 0b001
ALT1 IRQ[13] SIU External interrupt I 0b010
ALT2 DSPI_C_S DSPI LVDS+ clock O 0b100
GPIO GPIO[139] SIU GPIO I/O 0b000
S0x158
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 PA OBE
1
1
When configured as IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPU_A[26] and
GPIO[140] when configured as outputs.
IBE
2
2
When configured as IRQ, DSPI_C_SOUT_LVDS

or GPO, the IBE bit may be set to one to reflect the pin state in
the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. The IBE bit must be set
to one for both ETPU_A[26] and GPIO[140] when configured as inputs.
0 0 ODE HYS SRC WPE WPS
3
3
The weak pull up/down selection at reset for the ETPU_A[26] pin is determined by the WKPCFG pin.
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WKP
= Unimplemented or Reserved