NXP Semiconductors MPC5644A, Reference Manual, Page: 1408 / 1735

FlexCAN Module
MPC5644A Microcontroller Reference Manual, Rev. 6
1408 Freescale Semiconductor
Figure 32-8. Control Register (CR)
Base + 0x0004
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PRESDIV RJW PSEG1 PSEG2
W
RE-
SET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BOFFMSK
ERRMSK
CL
KSR
C
LPB
TW
RN
MSK
RWRNMSK
0 0
SMP
BOFFREC
TSYN LBUF
LOM
PROPSEG
W
RE-
SET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 32-10. CR Register field descriptions
Field Description
RESDIV Prescaler Division Factor
This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock)
frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value,
the Sclock frequency is equal to the CPI clock frequency. The maximum value of this register is
0xFF, that gives a minimum Sclock frequency equal to the CPI clock frequency divided by 256. For
more information refer to
Section 32.5.8.4, Protocol timing .
Sclock frequency = CPI clock frequency / (P 1)
PRJW Resync Jump Width
This 2-bit field defines the maximum number of time quanta
1
that a bit time can be changed by
one resynchronization.
The valid programmable values are 0 – 3.
Resync Jump Width = RJW + 1.
PSEG1 Phase Segment 1
This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time.
The valid programmable values are 0 – 7.
Phase Buffer Segment 1 = (PSEG1 + 1) x Time-Quanta.
PSEG2 Phase Segment 2
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid
programmable values are 1
– 7.
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.