NXP Semiconductors MPC5644A, Reference Manual, Page: 590 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
590 Freescale Semiconductor
18.4.4.2 ECC Status Register (ECSM_ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ECSM_ESR signals the last, properly-enabled memory event to be
detected. An ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is
asserted.
ECC interrupt generation is separated into single-bit error detection/correction, uncorrectable error
detection and the combination of the two as defined by the following boolean equations:
ECSM_ECC1BIT_IRQ
= ECSM_ECR[ER1BR] & ECSM_ESR[R1BC] // platform ram, 1-bit correction
| ECSM_ECR[EF1BR] & ECSM_ESR[F1BC] // platform flash, 1-bit correction
ECSM_ECCRNCR_IRQ
= ECSM_ECR[ERNCR] & ECSM_ESR[RNCE] // platform ram, noncorrectable error
ECSM_ECCFNCR_IRQ
= ECSM_ECR[EFNCR] & ECSM_ESR[FNCE] // platform flash, noncorrectable error
ECSM_ECC2BIT_IRQ
= ECSM_ECCRNCR_IRQ // platform ram, noncorrectable error
| ECSM_ECCFNCR_IRQ // platform flash, noncorrectable error
ECSM_ECC_IRQ
= ECSM_ECC1BIT_IRQ // 1-bit correction
| ECSM_ECC2BIT_IRQ // noncorrectable error
where the combination of a properly-enabled category in the ECSM_ECR and the detection of the
corresponding condition in the ECSM_ESR produces the interrupt request.
The ECSM allows a maximum of one bit of the ECSM_ESR to be asserted at any given time. This
preserves the association between the ECSM_ESR and the corresponding address and attribute registers,
which are loaded on each occurrence of a properly-enabled ECC event. If there is a pending ECC interrupt
and another properly-enabled ECC event occurs, the ECSM hardware automatically handles the
ECSM_ESR reporting, clearing the previous data and loading the new state and thus guaranteeing that
only a single flag is asserted.
To maintain the coherent software view of the reported event, the following sequence in the ECSM error
interrupt service routine is suggested:
1. Read the ECSM_ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two
values are different, go back to step 1 and repeat.
4. When the values are identical, write a ‘1’ to the asserted ESR flag to negate the interrupt request.