NXP Semiconductors MPC5644A, Reference Manual, Page: 806 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
806 Freescale Semiconductor
24.4.7.2 ETPU_CxSCR – eTPU Channel x Status Control Register
ETPU_CxSCR gathers the interrupt status bits of the channel, and also the Function Mode definition
(read-write). Bits CIS, CIOS and DTRS for each channel can be also accessed from ETPU_CISR,
ETPU_CIOSR and ETPU_CDTRSR registers respectively (see
Section 24.4.6, Global channel registers ).
Host must write 1 to clear a status bit.
Figure 24-22. ETPU_CxSCR Register
Offset: Channel_Registe 0x4 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CIS CIOS 0 0 0 0 0 0 DTR
S
DTR
OS
0 0 0 0 0 0
W CIC CIOC DTR
C
DTR
OC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IPS OPS OBE 0 0 0 0 0 0 0 0 0 0 0 FM
W
Reset 0/1
1
1
The IPS value after reset is MCU dependent
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 24-34. ETPU_CxSCR field description
Field Description
31 CIS—Channel Interrupt Status
1: channel has a pending interrupt to the Host CPU.
0: channel has no pending interrupt to the Host CPU.
31 CIC—Channel Interrupt Clear
1: clear interrupt status bit.
0: keep interrupt status bit unaltered.
These bits are mirrored in ETPU_CISR – see Section 24.4.6.1, ETPU_CISR – eTPU Channel Interrupt
Status Register . See also Section 24.5.9.3.10, Channel interrupt and data transfer requests .
30 CIOS—Channel Interrupt Overflow Status
1: interrupt overflow asserted for this channel
0: interrupt overflow negated for this channel