NXP Semiconductors MPC5644A, Reference Manual, Page: 1445 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1445
— Up to 255 entries for each FIFO
— Global frame ID filtering, based on both value/mask filters and range filters
— Global channel ID filtering
— Global message ID filtering for the dynamic segment
• 4 configurable slot error counters
• 4 dedicated slot status indicators
— Used to observe slots without using receive message buffers
• Measured value indicators for the clock synchronization
— internal synchronization frame ID and synchronization frame measurement tables can be
copied into the FlexRay memory area
• Fractional macroticks are supported for clock correction
• Maskable interrupt sources provided via individual and combined interrupt lines
• 1 absolute timer
• 1 timer that can be configured to absolute or relative
• SECDED for protocol engine data RAM
• SEDDED for CHI lookup table RAM
33.1.6 Modes of operation
This section describes the basic operational power modes of the CC.
33.1.6.1 Disabled mode
The CC enters the Disabled Mode during hard reset. The CC indicates that it is in the Disabled Mode by
negating the module enable bit MEN in the
Module Configuration Register (FR_MCR) .
In the Disabled Mode no communication is performed on the FlexRay bus.
All registers with the write access conditions Any Time and Disabled Mode can be accessed for writing as
stated in Section 33.5.2, Register descriptions” .
The application configures the CC by accessing the configuration bits and fields in the Module
Configuration Register (FR_MCR) .
33.1.6.1.1 Leave Disabled mode
The CC leaves the Disabled Mode and enters the Normal Mode, when the application writes 1 to the
module enable bit MEN in the
Module Configuration Register (FR_MCR)
NOTE
Once the CC is enabled it can only be disabled via a device reset.