NXP Semiconductors MPC5644A, Reference Manual, Page: 769 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 769
8 SCMERR—SCM Read Error
This flag indicates that an SCM read error occurred on a microengine read, generating a Global Exception.
Errors from Host reads neither set this flag nor generation Global Exceptions. This bit is cleared by writing
1 to GEC.
1: Global Exception requested by SCM read error is pending.
0: No Global Exception pending because of SCM read error.
9-10 Reserved
11-15 SCMSIZE[4:0]—SCM Size
This read-only field holds the number of 2 Kbyte SCM Blocks minus 1. This bit is write protected when any
of the engines are not halted or stopped
1
. When VIS = 1, the ETPU_ECR MDIS bits are write protected,
and only 32-bit aligned SCM writes are supported. The value written to SCM is unpredictable if other
transfer sizes are used.
16-19 Reserved
20 SCMMISC, SCMMISCC—SCM MISC Complete, SCM MISC Complete Clear
Flag SCMMISC indicates that MISC has completed the evaluation of the SCM signature since reset or the
since the last time it was cleared. SCMMISC is cleared by writing 1 to SCMMISCC (at same bit position),
and is not cleared when MISC is disabled (SCMMISEN = 0). SCMMISC asserts at the end of the SCM
memory scan, either if the signature matches or not.
1: MISC completed at least one SCM signature calculation and compare since the last time SCMMISC
was cleared.
0: MISC has not yet completed an SCM signature calculation and compare since the last time SCMMISC
was cleared.writes are supported. The value written to SCM is unpredictable if other transfer sizes are
used.
21 SCMMISF—SCM MISC Flag
The SCMMISF bit is set by the SCM MISC (Multiple Input Signature Calculator) logic to indicate that the
calculated signature does not match the expected value, at the end of a MISC iteration. See
Section 24.5.10, Test and Development Support , for more details.
1: MISC has read entire SCM array and the expected signature in ETPU_MISCCMPR does not match the
value calculated.
0: Signature mismatch not detected.
This bit is cleared when Global Exception is cleared by writing 1 to GEC.
22 SCMMISEN—SCM MISC Enable
The SCMMISEN bit is used for enabling/disabling the operation of the MISC logic. SCMMISEN is readable
and writable at any time. The MISC logic will only operate when this bit is set to 1. When the bit is reset
the MISC address counter is set to the initial SCM address. When enabled, the MISC will continuously
cycle through the SCM addresses, reading each and calculating a CRC. In order to save power, the MISC
can be disabled by clearing the SCMMISEN bit. See
Section 24.5.10, Test and Development Support , for
more details.
1: MISC operation enabled.
0: MISC operation disabled. The MISC logic is reset to its initial state.
SCMMISEN resets automatically when MISC logic detects an error, i.e., when SCMMISF transitions from
0 to 1, disabling the MISC operation.
23-24 Reserved
Table 24-5. ETPU_MCR field description
Field Description