NXP Semiconductors MPC5644A, Reference Manual, Page: 711 / 1735

Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 711
Figure 23-13. REACM Hold-off Timer Bank Registers (REACM_HOTBK)
23.3.12 REACM Threshold Bank Register (REACM_THBK)
The REACM Threshold Bank Register (REACM_THBK) holds the value to be used for comparison
against results received from the ADC. Based on that comparison the reaction channel decides the Channel
output value to be either HOD or LOD.
Figure 23-14. REACM Threshold Bank Register (REACM_THBK)
Address: REACM_BASE (0xC3FC_7000) + (from 0x0380 to 0x0388) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
HOLD_OFF[11:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 23-15. REACM_HOTBK field descriptions
Field Description
0–19 Reserved, should be cleared.
20–31
HOLD_OFF[11:0]
Hold-off Timer Value
The HOLD_OFFT[11:0] value is one element of the Hold-off Timer Register Bank. Up to three
values can be stored within the Hold-off Timer Bank.
Note: When using the hold-off timer for sequence advance, the counted time (considering
prescaler) must be greater than 64 clock cycles.
Address: REACM_BASE (0xC3FC_7000) + (from 0x0400 to 0x045C) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
THRESHOLD_VALUE[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0