NXP Semiconductors MPC5644A, Reference Manual, Page: 1296 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1296 Freescale Semiconductor
devices, requiring control and data fields in the frame. Control field may come from DSPI_ASDR, set by
the device’s CPU, while data field can be generated by device peripheral modules, such as PWM timers.
A copy of the last 32-bit DSI frame shifted out of the Shift Register is stored in the DSPI DSI Transmit
Comparison Register (DSPI_COMPR). This register provides added visibility for debugging and it serves
as a reference for transfer initiation control.
Figure 30-31 shows the DSI Serialization logic.
Figure 30-31. DSI serialization diagram
30.9.3.4 DSI deserialization
When all bits in a DSI frame have been shifted in, the frame is copied to the DSPI DSI Deserialization
Data Register (DSPI_DDR). This register presents the deserialized data as Parallel Output signal values.
The DSPI_DDR is memory mapped to allow host software to read the deserialized data directly.
The received data is bit-wise compared to the value of the DSI Deserialized Data Polarity Interrupt
Register, bit-wise AND’ed with DSI Deserialized Interrupt Mask Register and the results OR’ed to
produce the DDIF flag in the DSPI_SR, which in turn can cause a DDI interrupt request if the DDIFRE
bit of DSPI_RSER is set.
Figure 30-32 shows the DSI deserialization logic.
DSI Config.
SOUT
Shift Register
HT
0 1
Clock
Logic
SCK
TXSS
0
1
Register
Control
Logic
DSI Transmit
Comparison Register
PCS
DSI S
e
rial
iz
a
tio
n
D
a
ta
Regist
er
32
32
32
Parallel
Inputs 32
32 x
16
t
o
1 Muxes
DSPI Parallel Inputs
Select Registers 0-3
DSPI Alternate
Serialization Data Register
Slave Bus Interface
DSI Serialization
Source Register
32
N