NXP Semiconductors MPC5644A, Reference Manual, Page: 599 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 599
18.4.4.8 RAM ECC Address Register (ECSM_REAR)
The ECSM_REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in
the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the ECSM_REAR,
ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and the appropriate flag
(RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x58, +0x5C ( (0xFFF4_0058, 0xFFF4_005C)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FEDH[31:16]
W
Reset — — — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEDH[15:0]
W
Reset — — — — — — — — — — — — — — — —
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
R FEDL[31:16]
W
Reset — — — — — — — — — — — — — — — —
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R FEDL[15:0]
W
Reset — — — — — — — — — — — — — — — —
= Unimplemented
Figure 18-10. Flash ECC Data Register (ECSM_FEDRH, ECSM_FEDRL)
Table 18-12. ECSM_FEDR field description
Name Description
0–63
FEDH[31:0]
FEDL[31:0]
Flash ECC Data Register
This 64-bit register contains the data associated with the faulting access of the last,
properly-enabled flash ECC event. The register contains the data value taken directly from the data
bus.