NXP Semiconductors MPC5644A, Reference Manual, Page: 751 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 751
When the SCM is implemented by RAM, the Host must first initialize it with the proper microcode
program prior to enabling any eTPU Function, and then enable eTPU access (which also disables Host
access).
24.2.1.1.4 Shared parameter RAM (SPRAM)
The SPRAM works as data RAM which can be accessed by the Host CPU and up to two eTPU engines.
This memory is used for information transfer between the Host CPU and the eTPU, as data storage for the
eTPU microcode program or for communication between the two eTPU engines. SPRAM width is 32 bits,
and is accessible by the Host as byte, 16-bit or 32-bit wide. eTPU can access it as full 32 bits, lower 24 bits
or upper byte (8-bit).
The host can also access the SPRAM space mirrored in other area with Parameter Signal Extension (PSE).
Parameter Signal Extension accesses differ from the usual host accesses to the original SPRAM area as
follows:
• Writes are effective only to the lower 3 bytes of a word: the word’s most significant byte is kept
unaltered in SPRAM.
• Reads return the lower 3 bytes of a word sign-extended to 32 bits, i.e.: the most significant bit of
the word s 2nd most significant byte is copied in all 8 bits of the most significant read byte.
Each eTPU channel can be associated with a variable number of parameters located in the SPRAM,
according to its selected Function. In addition, the SPRAM can be fully shared between two eTPU engines,
enabling direct communication between them.
High flexibility of the SPRAM utilization is achieved as follows:
• Each channel has a programmable base address pointing to the address of its first parameter with
two parameter granularity. This way the SPRAM can be partitioned according to the actual
function needs.
• The microcode can access the first 128 parameters of the selected channel in channel relative
access mode.
• Each engine can access all the SPRAM address space in indirect addressing mode. Blocks of data
are easily transferred using stack operation.
• Absolute addressing mode can access the first 256 parameters (TPU3 functionality), implementing
a shared pool of parameters holding global variables.
In the Host address space each parameter occupies four bytes. eTPU usage of the upper byte is achieved
by having a 32-bit P register which can access the upper byte, the lower 24 bits or all the 32 bits. The
microcode can switch between access sizes at any time.
Each Function may require a different number of parameters. During the eTPU initialization the Host has
to program channel base addresses, allocating proper parameters for each channel according to its selected
Function.
24.2.1.1.5 Scheduler
Out of reset, all channels are disabled. The Host CPU makes a channel active by assigning it one of three
priorities: high, middle, or low. The Scheduler determines the order in which channels are serviced based