NXP Semiconductors MPC5644A, Reference Manual, Page: 117 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 117
Chapter 6
Device Performance Optimization
6.1 Introduction
The MPC5644A contains several features that can influence the overall level of performance provided by
the device.
Some of these features may be initialized upon negation of reset either by a software program called the
Boot Assist Module (BAM), by a hardware state machine or by appropriate default register settings.
Although the device exits the reset state into a functional state it does not necessarily have the default
optimum performance settings for any given application.
This chapter provides guidance for users to fully optimize their application to achieve the highest possible
performance from the MPC5644A. It provides a description of the areas that should be focused on when
optimizing an application for performance by describing the features and recommending settings to be
applied. It focuses on hardware configurations although certain aspects of the application software such as
compiler settings and optimizations will be discussed.
6.2 Features
The MPC5644A has the following hardware features that can be configured to impact the overall
performance of the device:
• Branch Prediction
— Branch Target Buffer
— Branch Prediction Control
• Frequency-modulated PLL
• Flash Bus Interface Unit
— Flash access wait state and address pipelining control
— Flash instruction prefetching
— Flash data prefetching
• Crossbar switch
• System Cache
— Instruction Cache
• Memory Management Unit
Further application level features can impact the application performance:
• Hardware Single Precision Floating point
• Signal Processing Extension (SPE-APU)
• Variable Length Encoding (VLE)
• Compiler optimizations
Further factors that impact the overall application performance are the use of the intelligent peripherals: