NXP Semiconductors MPC5644A, Reference Manual, Page: 261 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 261
NOTE
The programming model can only be referenced using 32-bit (word)
accesses. Attempted references using different access sizes, to undefined
(reserved) addresses, or with a non-supported access type (for example, a
write to a read-only register or a read of a write-only register) generate a bus
error termination.
13.4.2.1 MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status and three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
Address: MPU_BASE (0xFFF1_0000) + 0x0000 Access: Supervisor
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SPERR[0:7]
1
1
Each SPERR bit can be cleared by writing a one to the bit location.
HRL
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NSP NRGD
VLD
W
Reset 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
= not implemented
Figure 13-1. MPU Control/Error Status Register (MPU_CESR)
Table 13-3. MPU_CESR field descriptions
Field Description
0–7
SPERR
Slave Port n
1
Error, where the slave port number matches the bit number
Each bit in this read-only field represents a flag maintained by the MPU for signaling the presence of a
captured error contained in the MPU_EAR
n and MPU_EDR n registers. The individual bit is set when the
hardware detects an error and records the faulting address and attributes. It is cleared when the
corresponding bit is written to a logical one. If another error is captured at the exact same cycle as a write
of a logical one, this flag remains set. A find-first-one instruction (or equivalent) can be used to detect the
presence of a captured error.
0 The corresponding MPU_EAR
n /MPU_EDR n registers do not contain an unread captured error
1 The corresponding MPU_EAR n /MPU_EDR n registers do contain an unread captured error
Note: Bit 0 indicates an SRAM access protection error and bit 1 a peripheral bridge protection error.
12–15
HRL
Hardware Revision Level
This 4-bit read-only field specifies the MPU’s hardware and definition revision level. It can be read by
software to determine the functional definition of the module. This field reads as 0 on MPC5644A.