NXP Semiconductors MPC5644A, Reference Manual, Page: 196 / 1735

Multi-Layer AHB Crossbar Switch (XBAR)
MPC5644A Microcontroller Reference Manual, Rev. 6
196 Freescale Semiconductor
9.2.2 XBAR register descriptions
The following paragraphs provide detailed descriptions of the various XBAR registers.
Refer to Figure 9-2 for the various bit configurations that appear in the register maps.
Table 9-2. XBAR Register Configuration Summary
Address Register Location
XBAR_Base (0xFFF0_4000) MPR0 — Master Priority Register for Slave port 0 on page
9-197
XBA 0x004 –
XBA 0x00F Reserved —
XBA 0x010 SGPCR0 — General Purpose Control Register for
Slave port 0
on page
9-199
XBA 0x014 –
XBA 0x0FF Reserved —
XBA 0x100 MPR1 — Master Priority Register for Slave port 1 on page
9-197
XBA 0x104 –
XBA 0x10F Reserved —
XBA 0x110 SGPCR1 — General Purpose Control Register for
Slave port 1
on page
9-199
XBA 0x114 –
XBA 0X1FF Reserved —
XBA 0x200 MPR2 — Master Priority Register for Slave port 2 on page
9-197
XBA 0x204 –
XBA 0x20F Reserved —
XBA 0x210 SGPCR2 — General Purpose Control Register for
Slave port 2
on page
9-199
XBA 0x214 –
XBA 0X6FF Reserved —
XBA 0x700 MPR7 — Master Priority Register for Slave port 7 on page
9-197
XBA 0x704 –
XBA 0X70F Reserved —
XBA 0x710 SGPCR7 — General Purpose Control Register for
Slave port 7
on page
9-199
XBA 0x714 –
XBA 0XF03 Reserved —
Always
reads 1
1 Always
reads 0
0 R/W
bit
BIT
1
1
“BIT” refers to a field name in the register. Some fields span multiple bits.
Read-
only bit
BIT
1
Write-
only bit
Write 1
to clear
BIT
1
Self-clear
bit
0 N/A
BIT
1
w1c BIT
1
Figure 9-2. Key to Register Fields