NXP Semiconductors MPC5644A, Reference Manual, Page: 576 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
576 Freescale Semiconductor
3. If required, program the FMPLL_SYNFMMR with desired FM parameters, poll the BSY bit until it negates, then enable
FM by asserting the MODEN bit.
4. Engage normal mode by writing to FMPLL_ESYNCR1[CLKCFG].
17.5.3 Lock detection
A pair of counters monitor the reference and feedback clocks to determine when the system has acquired frequency lock. Once
the FMPLL has locked, the counters continue to monitor the reference and feedback clocks and will report if/when the FMPLL
has lost lock. The FMPLL registers provide the flexibility to select whether to generate an interrupt, assert system reset or do
nothing in the event that the FMPLL loses lock.
Loss-of-lock reset and interrupt are only generated when the FMPLL is operating in normal mode. The LOCF bit is not asserted
by a loss-of-lock condition detected during bypass, although going to bypass mode from normal mode does not automatically
clear the flag if it was asserted while the FMPLL was in normal mode.
17.5.4 Loss-of-clock detection
The FMPLL reference and output clocks may be continuously monitored by a module called Clock
Quality Monitor (CQM), shown in
Figure 17-7 . The intent of the CQM is to assure that the system bus
clock is created from good clock sources. Whether the clocks are monitored or not is determined by the
clock operating mode and control bits in the FMPLL registers, as shown in
Table 17-12 .
In bypass mode with crystal reference, the reference clock is always monitored, regardless of the state of
the LOCEN bit. In bypass mode with external reference, the reference clock is not monitored, regardless
of the state of the LOCEN bit. This is done so that the whole device frequency range can be sourced from
the external clock generator when using external reference mode. The FMPLL output may only monitored
in normal mode, depending on the state of the LOCEN bit.
The clock quality monitor uses an internal 4 MHz RC oscillator as a reference time base to measure the
frequency of the crystal oscillator and the FMPLL output. The frequency of these clocks are expected to
be within the following frequency ranges:
• Reference clock must be within the crystal frequency range
1
• PLL output must be above 1.5 MHz (minimum VCO free-running frequency divided by the
maximum ERFD)
In the event either of the clocks fall outside the expected window, a loss of clock condition is reported. The
FMPLL can be programmed to switch the system clock to a backup clock in the event of such a failure.
Additionally, the user may select to have the system enter reset, assert an interrupt request, or do nothing
if/when the FMPLL reports this condition.
1. See Section 17.1, Information specific to this device , for information on crystal frequencies supported.