NXP Semiconductors MPC5644A, Reference Manual, Page: 110 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
110 Freescale Semiconductor
after power-on reset the Clock Quality Monitor (CQM) inhibits the system clock and keep system reset
asserted while the crystal oscillator has not stabilized. The PLLREF pin must be kept stable during the
whole period while system reset is asserted.
5.3.4.1 Bypass mode with crystal reference
In the bypass mode with crystal reference, the FMPLL is completely bypassed and the system clock is
driven from the crystal oscillator. The user must supply a crystal that is within the appropriate frequency
range, the crystal manufacturer recommended external support circuitry, and short signal route from the
MCU to the crystal.
In bypass mode the PLL itself may or may not be running, depending on the state of the CLKCFG[1] bit
of the FMPLL_ESYNCR1 register, but the PLL output is not connected to the system clock. Consequently,
frequency modulation is not available. The pre-divider is also bypassed, but the system clock divider
(SYSDIV) can be used to reduce the system clock frequency. The system clock divider can be programmed
by writing to SIU_ SYSDIV[SYSDIV].
Bypass mode with crystal reference is the default mode at reset if the PLLREF pin is driven high. After
reset, this mode can be entered by programming FMPLL_ESYNCR1[CLKCFG] as shown in
Table 5-1 .
Figure 5-3. Bypass mode with crystal reference
5.3.4.2 Bypass mode with external reference
The bypass mode with external reference functions the same as bypass mode with crystal reference, except
that the system clock is driven by an external clock generator connected to the EXTAL pin, rather than a
crystal oscillator. The input frequency range is the same and frequency modulation is not available.
Bypass mode with external reference is the default mode at reset if the PLLREF pin is driven low. After
reset, this mode can be entered by programming FMPLL_ESYNCR1[CLKCFG] as shown in
Table 5-1 .
0
1
0
1
XTAL OSC
FMPLL
XTAL
EXTAL
PLLREF
clkcfg[0]
SYSDIV
/2, /4, /8, /16
bypass_sysdiv
siu_system_div[1:0]
IDF
PD
ODF NDIV Lock
Control & Status Registers
PHI
CLKIN
Clock Quality Monitor
(CQM)
loss of
VCO loss of
Reference
system
clock
RCOSC