NXP Semiconductors MPC5644A, Reference Manual, Page: 1168 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1168 Freescale Semiconductor
Figure 25-101.
EQADC
System Overview
The EQADC system consists of four parts: queues in RAM, the EQADC, on-chip ADCs, and an external
device. As compared with the QADC, the EQADC system requires two pieces of extra hardware.
1. A DMA or an MCU is required to move data between the EQADC’s FIFOs and Queues in the
system memory.
2. A serial interface (EQADC Synchronous Serial Interface - EQADC SSI) is implemented to
transmit and receive data between the EQADC and the external device.
Since there are only FIFOs inside the EQADC, much of the terminology or use of the register names,
register contents, and signals of the EQADC involve “FIFO” instead of “Queue”. These register names,
register contents, and signals are functionally equivalent to the “Queue” counterparts in the QADC.
Table 25-78 lists how the EQADC register, register contents, and signals are related to QADC.
External
Triggers
CQueues RQueues DMAC/CPU
DMA/Interrupt
Requests
EQADC
Trigger and
FIFO Control
Logic
System Bus
Analog to Digital Converter
CFIFOs RFIFOs
Analog to Digital Converter
EQADC SSI
External
Device
Serial
Connection