NXP Semiconductors MPC5644A, Reference Manual, Page: 671 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 671
Figure 22-25. DAOC with transfer disabling example
22.5.1.1.7 Modulus counter buffered (MCB) mode
The MCB mode provides a time base which can be shared with other channels through the internal counter
buses. Register A1 is double buffered thus allowing smooth transitions between cycles when changing A2
register value on the fly. A1 register is updated at the cycle boundary, which is defined as when the internal
counter transitions to 0x1.
The internal counter values operates within a range from 0x1 up to register A1 value. If when entering
MCB mode exiting from GPIO mode the internal counter value is not within that range then the A match
will not occur causing the channel internal counter to wrap at the maximum counter value which is
0xFF_FFFF for a 24-bit counter. After the counter wrap occurs it returns to 0x1 and resume normal MCB
mode operation. Thus in order to avoid the counter wrap condition make sure its value is within the 0x1
to A1 register value range when the MCB mode is entered.
MODE[6] bit selects internal clock source if cleared or external if set. When external clock is selected the
input channel pin is used as the channel clock source. The active edge of this clock is defined by EDPOL
and EDSEL bits in the EMIOS_CCR[n].
When entering MCB mode, if the up counter is selected by MODE[4] = 0 (MODE[0:6] = 101000b), the
internal counter starts counting from its current value to up direction until A1 match occurs. The internal
counter is set to 0x1 when its value matches A1 value and a clock tick occurs (either prescaled clock or
input pin event).
selected counter bus 0x0 0x2
FLAG set event
A1 value
2
0xx
output flip-flop
2. CADR[n] = A1 (when reading)
0x0 0x2 0x1 0x2 0x0 0x1 0x1
FLAG pin/register
FLAG clear
EDSEL = 1
System Clock
enabled A1 match
EDPOL = x
B2 value
5
0x2
B1 value
4
0xx
A2 value
3
0x1
OU
1
enabled B1 match
0x1
0xx
0xx
0x2
0x1
write to A2
0x2
0x2
0x1
0x2
0x1
0x1
0x2
write to B2
write to A2
write to B2
write to A2
write to B2
MODE[0] = 1
3. CADR[n] = A2 (when writing)
4. CBDR[n] = B1 (when reading)
5. CBDR[n] = B2 (when writing)
Note: 1. OU[n] bit of the OUDR