NXP Semiconductors MPC5644A, Reference Manual, Page: 154 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
154 Freescale Semiconductor
8.3.2.4 eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
The EDMA_EEIRH and EDMA_EEIRL provide a bitmap for the 32 (or 64 for eDMA) channels to enable
the error interrupt signal for each channel. EDMA_EEIRH supports channels 63–32, while
EDMA_EEIRL covers channels 31–0.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and
EDMA_CEEIR are provided so that the error interrupt enable for a single channel can be modified without
the performing a read-modify-write sequence to the EDMA_EEIRH and EDMA_EEIRL.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted.
Address: EDM 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EEI63 EEI62 EEI61 EEI60 EEI59 EEI58 EEI57 EEI56 EEI55 EEI54 EEI53 EEI52 EEI51 EEI50 EEI49 EEI48 W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI47 EEI46 EEI45 EEI44 EEI43 EEI42 EEI41 EEI40 EEI39 EEI38 EEI37 EEI36 EEI35 EEI34 EEI33 EEI32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH)
Address: EDM 0x0014 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EE
I3
1
EE
I3
0
EE
I2
9
EE
I2
8
EE
I2
7
EE
I2
6
EE
I2
5
EE
I2
4
EE
I2
3
EE
I2
2
EE
I2
1
EE
I2
0
EE
I1
9
EE
I1
8
EE
I1
7
EE
I1
6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EEI15 EEI14 EEI13 EEI12
EEI1
1
EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)