NXP Semiconductors MPC5644A, Reference Manual, Page: 1035 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1035
Table 25-15.
EQADC
FIFO and Interrupt Status Register x (
EQADC
_FISRx) field description
Field Description
0
NCFx
Non-Coherency Flag
NCFx is set whenever a command sequence being transferred through CFIFOx becomes
non coherent. If NCIEx in
Section 25.5.2.8, EQADC Interrupt and DMA Control Registers
(EQADC_IDCR) , and NCF x are asserted, an interrupt request will be generated. Write “1” to
clear NCFx. Writing a “0” has no effect. For more information refer to Section 25.6.4.7.5,
Command Sequence Non-Coherency Detection .
1 Command sequence being transferred by CFIFOx became non-coherent.
0 Command sequence being transferred by CFIFOx is coherent.
1
TORFx
Trigger Overrun Flag for CFIFOx
TORFx
is set when trigger overrun occurs for the specified CFIFO in edge or level trigger
mode. Trigger overrun occurs when an already triggered CFIFO receives an additional
trigger. When TORIE
x in Section 25.5.2.8, EQADC Interrupt and DMA Control Registers
(EQADC_IDCR) , and TORF x are asserted, an interrupt request will be generated.
Apart from generating an independent interrupt request for a CFIFOx Trigger Overrun event,
the EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt,
the Command FIFO Underflow Interrupt, and the Command FIFO Trigger Overrun Interrupt
requests of ALL CFIFOs are ORed. When RFOIEx, CFUIEx, and TORIEx are all asserted,
this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See
Section 25.6.8, EQADC DMA/Interrupt request , for details.
Write “1” to clear the TORF x bit. Writing a “0” has no effect.
1 Trigger overrun occurred.
0 No trigger overrun occurred.
Note: The trigger overrun flag will not set for CFIFOs configured for software trigger mode.