NXP Semiconductors MPC5644A, Reference Manual, Page: 1266 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1266 Freescale Semiconductor
Table 30-7. DSPI_CTARn field description in master mode
Field Descriptions
0
DBR
Double Baud Rate
The DBR bit doubles the effective baud rate of the Serial Communications Clock (SCK). This field is
only used in master mode. It effectively halves the Baud Rate division ratio supporting faster
frequencies and odd division ratios for the Serial Communications Clock (SCK). When the DBR bit
is set, the duty cycle of the Serial Communications Clock (SCK) depends on the value in the Baud
Rate Prescaler and the Clock Phase bit as listed in
Table 30-8 . See the BR field description for details
on how to compute the baud rate.
0 The baud rate is computed normally with a 50/50 duty cycle
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler
1–4
FMSZ[0:3]
Frame Size
The number of bits transferred per frame is equal to FMSZ field value plus 1. Minimum valid FMSZ
field value is 3.
When operating in TSB mode, detailed in
Section 30.9.8, Timed serial bus (TSB), the FMSZ field
value plus 1 is equal the data frame bit number, where control of the PCS assertion switches from
the DSPI_DSICR to the DSPI_DSICR1 register.
5
CPOL
Clock Polarity
The CPOL bit selects the inactive state of the Serial Communications Clock (SCK). This bit is used
in both master and slave mode. For successful communication between serial devices, the devices
must have identical clock polarities. When the Continuous selection format is selected, switching
between clock polarities without stopping the DSPI can cause errors in the transfer due to the
peripheral device interpreting the switch of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
6
CPHA
Clock Phase
The CPHA bit selects which edge of SCK causes data to change and which edge causes data to be
captured. This bit is used in both master and slave mode. For successful communication between
serial devices, the devices must have identical clock phase settings. In Continuous SCK mode or
TSB mode the bit value is ignored and the transfers are done as CPHA bit is set to 1.
0 Data is captured on the leading edge of SCK and changed on the following edge
1 Data is changed on the leading edge of SCK and captured on the following edge
7
LSBFE
LSB First
The LSBFE bit selects if the LSB or MSB of the frame is transferred first. When operating in TSB
configuration, this bit should be set to be compliant to MSC specification.
0 Data is transferred MSB first
1 Data is transferred LSB first
8–9
PCSSCK[0:1
]
PCS to SCK Delay Prescaler
The PCSSCK field selects the prescaler value for the delay between assertion of PCS and the first
edge of the SCK. See the CSSCK field description how to compute the PCS to SCK delay. In the TSB
mode the PCSSCK field has no effect.
00 PCS to SCK prescaler value is 1
01 PCS to SCK prescaler value is 3
10 PCS to SCK prescaler value is 5
11 PCS to SCK prescaler value is 7