External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
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Accesses to devices operating without a chip select are always single beat. If an internal request to the EBI
indicates a size of less than 32 bytes, the request is fulfilled by running one or more single-beat external
transfers, not by an external burst transfer.
An 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of
the words (doubleword aligned) and requiring the memory device to sequentially drive each word on the
data bus. The selected slave device must internally increment ADDR[27:29] (also ADDR30 in the case of
a 16-bit port size device) of the supplied address for each transfer, until the address reaches an 8-word
boundary, and then wrap the address to the beginning of the 8-word boundary. The address and transfer
attributes supplied by the EBI remain stable during the transfers. Termination of each beat transfer occurs
by the EBI asserting TA (SETA=1 is not supported for burst transfers). The EBI requires that addresses be
aligned to a doubleword boundary on all burst cycles.
shows the burst order of beats returned for an 8-word burst to a 32-bit port.
The general case of burst transfers assumes that the external memory has 32-bit port size and 8-word burst
length. The EBI can also burst from 16-bit port size memories, taking twice as many external beats to fetch
the data as compared to a 32-bit port with the same burst length. The EBI can also burst from 16-bit or
32-bit memories that have a 4-word burst length (BL=1 in the appropriate Base Register). In this case, two
external 4-word burst transfers (wrapping on 4-word boundary) are performed to fulfill the internal 8-word
request
1
. This operation is considered atomic by the EBI, so the EBI does not allow other unrelated master
accesses or bus arbitration to intervene between the transfers. For more details and a timing diagram, see
Section 14.5.2.6.3, Small access example #3: 32-byte read to 32-bit port with BL=1
.
During burst cycles, the BDIP (Burst Data In Progress) signal is used to indicate the duration of the burst
data. During the data phase of a burst read cycle, the EBI receives data from the addressed slave. If the
EBI needs more than one data, it asserts the BDIP signal. Upon receiving the data prior to the last data, the
EBI negates BDIP. Thus, the slave stops driving new data after it receives the negation of BDIP on the
rising edge of the clock. Some slave devices have their burst length and timing configurable internally and
thus may not support connecting to a BDIP pin. In this case, BDIP is driven by the EBI normally, but the
output is ignored by the memory and the burst data behavior is determined by the internal configuration
of the EBI and slave device. When the TBDIP bit is set in the appropriate Base Register, the timing for
BDIP is altered. See
Section 14.5.2.5.1, TBDIP effect on burst transfer
for this timing.
Since burst writes are not supported by the EBI
2
, the EBI negates BDIP during write cycles.
1.
Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See
Non-chip-select burst in 16-bit data bus mode
Table 14-12. Wrap Bursts Order
Burst Starting Address
ADDR[27:28]
Burst Order
(Assuming 32-bit Port Size)
00
word0
word1
word2
word3
word4
word5
word6
word7
01
word2
word3
word4
word5
word6
word7
word0
word1
10
word4
word5
word6
word7
word0
word1
word2
word3
11
word6
word7
word0
word1
word2
word3
word4
word5
1.
This case (of 2 external burst transfers being required) applies only to AMBA data bus width of 64 bits.
2.
Except for the special case of a 32-bit non-chip-select access in 16-bit data bus mode. See
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